peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 138

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

FALC56 V1.2
PEB 2256
Functional Description T1/J1
BOM receiver have been switched on (MODE.HRAC/BRAC), an automatic switching
between HDLC and BOM mode is enabled. If eight or more consecutive ones are
detected, the BOM mode is entered. Upon detection of a flag in the data stream, the
FALC56 switches back to HDLC mode. In BOM mode, the following byte format is
assumed (the left most bit is received first): 111111110xxxxxx0
Three different BOM reception modes can be programmed (CCR1.BRM+ CCR2.RBFE).
If CCR2.RFBE is set, the BOM receiver accepts only BOM frames after detecting 7 out
of 10 equal BOM pattern. Buffering of receive data is done in a 64 byte deep RFIFO.
5.1.14.6 4 kbit/s Data Link Access in F72 Format (T1/J1)
The DL-channel protocol is supported as follows:
• access is done on a multiframe basis through registers RDL(3:1),
• the DL-bit information from frame 26 to 72 is stored in the receive FIFO of the signaling
controller.
Data Sheet
138
2002-08-27