peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 442

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

LA2
Signaling Status Register 3 (Read)
Value after reset: 00
SIS3
XDOV3
XFW3
XREP3
RLI3
CEC3
Data Sheet
XDOV3
7
Low Byte Address Compare - HDLC Channel 2
Significant in HDLC modes only.
The low byte address of a 2-byte address field, or the single address
byte of a 1-byte address field is compared with two registers. (RAL1,
RAL2).
0 =
1 =
Transmit Data Overflow - HDLC Channel 3
More than 32 bytes have been written to the XFIFO3.
This bit is reset
– by a transmitter reset command XRES or
– when all bytes in the accessible half of the XFIFO3 have been
Transmit FIFO Write Enable - HDLC Channel 3
Data can be written to the XFIFO3.
Transmission Repeat - HDLC Channel 3
Status indication of CMDR3.XREP3.
Receive Line Inactive - HDLC Channel 3
Neither flags as interframe time fill nor frames are received via the
signaling time slot.
Command Executing - HDLC Channel 3
0 =
written to.
1 =
executed, no further command can be temporarily written in CMDR4
register.
Note: CEC3 will be active at most 2.5 periods of the current system
data rate.
XFW3
H
moved in the inaccessible half.
RAL2 has been recognized
RAL1 has been recognized
No command is currently executed, the CMDR4 register can be
A command (written previously to CMDR4) is currently
XREP3
442
RLI3
CEC3
T1/J1 Registers
FALC56 V1.2
0
PEB 2256
2002-08-27
(9A)