peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 132

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 31
Buffer Size
(SIC1.RBS1/0)
bypass
short buffer
1 frame
2 frames
1)
Figure 47
A slip condition is detected when the write pointer (W) and the read pointer (R) of the
memory are nearly coincident, i.e. the read pointer is within the slip limits (S +, S –). If a
slip condition is detected, a negative slip (one frame or one half of the current buffer size
is skipped) or a positive slip (one frame or one half of the current buffer size is read out
twice) is performed at the system interface, depending on the difference between RCLK
and the current working clock of the receive backplane interface, i.e. on the position of
pointer R and W within the memory. A positive/negative slip is indicated by the interrupt
status bits ISR3.RSP and ISR3.RSN.
Data Sheet
In bypass mode the clock provided on pin SCLKR is ignored. Clocking is done with RCLK.
1)
gives an idea of operation of the receive elastic buffer:
Receive Buffer Operation Modes (T1/J1)
TS Offset program.
(RC1/0) + SYPR = input
disabled
not recommended,
recommended:
SYPR = output
not recommended,
recommended:
SYPR = output
enabled
132
Functional Description T1/J1
Slip perform.
no
yes
yes
yes
FALC56 V1.2
PEB 2256
2002-08-27