peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 418

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

CRC Error Counter (Read)
CECL
CECH
CR(15:0)
Data Sheet
CR15
CR7
7
7
CRC Errors
No function if CRC6 procedure or ESF format are disabled.
In ESF mode, the 16-bit counter is incremented when a multiframe
has been received with a CRC error. CRC errors are not counted
during asynchronous state. The error counter does not roll over.
During alarm simulation, the counter is incremented once per
multiframe.
Clearing and updating the counter is done according to bit
FMR1.ECM.
If this bit is reset the error counter is permanently updated in the
buffer. For correct read access of the error counter bit DEC.DCEC
has to be set. With the rising edge of this bit updating the buffer is
stopped and the error counter is reset. Bit DEC.DCEC is
automatically reset with reading the error counter high byte.
If FMR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error
counter state should be read within the next second.
418
T1/J1 Registers
FALC56 V1.2
CR0
CR8
0
0
PEB 2256
2002-08-27
(54)
(55)