peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 200

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Table 56
MODE = 88
MODE2= 88
MODE3= 88
CCR1 = 18
CCR3= 08
CCR4= 08
IMR0.RME = 0
IMR0.RPF = 0
IMR1.XPR = 0
IMR4.RME2=0
IMR4.RPF2=0
IMR5.XPR2=0
IMR5.RME3=0
IMR5.RPF3=0
IMR5.XPR3=0
RTR4.0 = 1
TTR4.0 = 1
TSEO = 00
TSBS1 = FF
TSBS2= FF
TSBS3= FF
TSS2= 01
TSS3= 02
Table 57
FMR5.EIBR = 1
IMR1.CASE = 0
IMR0.RSC = 0
Note: After the device initialization a software reset should be executed by setting of bits
Data Sheet
CMDR.XRES/RRES.
H
H
H
H
H
H
H
H
H
H
H
H
HDLC Controller Initialization (T1/J1)
Initialization of the CAS-BR Controller (T1/J1)
HDLC channel 1 receiver active, no address comparison.
HDLC channel 2 receiver active, no address comparison.
HDLC channel 2 receiver active, no address comparison.
Enable signaling via TS(24:1), interframe time fill with continuous
flags (channel 1).
Interframe time fill with continuous flags (channel 2).
Interframe time fill with continuous flags (channel 3).
Unmask interrupts for HDLC processor requests.
Select time slot 24 for HDLC data reception and transmission.
Even and odd frames are used for HDLC reception and
transmission.
Select all bits of selected time slot (channel 1).
Select all bits of selected time slot (channel 2).
Select all bits of selected time slot (channel 3).
Select time slot 1 for HDLC channel 2.
Select time slot 2 for HDLC channel 3.
Enable CAS-BR Mode
Send CAS-BR information stored in XS(12:1)
Enable interrupts which indicate the access to the XS(12:1) CAS-
BR registers and any data change in RS(12:1)
200
Operational Description T1/J1
FALC56 V1.2
PEB 2256
2002-08-27