peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 396

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

HRAC2
DIV2
Mode Register 3 (Read/Write)
Value after reset: 00
MODE3
MDS3(2:0)
HRAC3
Data Sheet
MDS32
7
MDS31
Receiver Active - HDLC Channel 2
Switches the HDLC receiver to operational or inoperational state.
0 =
1 =
Data Inversion - HDLC Channel 2
Setting this bit will invert the internal generated HDLC data stream.
0 =
1 =
Mode Select - HDLC Channel 3
The operating mode of the HDLC controller is selected.
000 = Reserved
001 = Reserved
010 = One-byte address comparison mode (RAL1, 2)
011 = Two-byte address comparison mode (RAH1, 2 and RAL1, 2)
100 = No address comparison
101 = One-byte address comparison mode (RAH1, 2)
110 = Reserved
111 = No HDLC framing mode 1
Receiver Active - HDLC Channel 3
Switches the HDLC receiver to operational or inoperational state.
0 =
1 =
H
Receiver inactive
Receiver active
Normal operation, HDLC data stream not inverted
HDLC data stream inverted
Receiver inactive
Receiver active
MDS30
396
HRAC3
DIV3
T1/J1 Registers
FALC56 V1.2
0
PEB 2256
2002-08-27
(8F)