peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 235

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

Transmit Spare Bits (Read/Write)
Value after reset: 00
XSP
CASEN
TT0
EBP
AXS
Data Sheet
7
CASEN
Channel Associated Signaling Enable
0 =
1 =
Time slot 0 Transparent Mode
0 =
1 =
E-Bit Polarity
0 =
1 =
Automatic Transmission of Submultiframe Status
Only applicable to CRC multiframe.
0 =
1 =
H
Normal operation.
A one in this bit position causes the transmitter to send the CAS
information stored in the XS(16:1) registers or serial CAS data
in the corresponding time slots.
Normal operation.
All information for time slot 0 on port XDI is inserted in the
outgoing pulseframe. All internal information of the FALC56
(framing, CRC, S
This function is mainly useful for system test applications (test
loops). Priority sequence of transparent modes: XSP.TTO >
TSWM.
In the basic- and multiframe asynchronous state the E-bit is
cleared.
In the basic- and multiframe asynchronous state the E-bit is set.
If automatic transmission of submultiframe status is enabled by
setting bit XSP.AXS and the receiver has lost synchronization,
the E-bit with the programmed polarity is inserted automatically
in S
condition that time slot 0 transparent mode and transparent S
bit in service word are both disabled).
Normal operation.
Information of submultiframe status bits RSP.SI1 and RSP.SI2
are inserted automatically in S
CRC multiframe (RSP.SI1 → S
S
i
-bit of frame 15). Contents of XSP.XS13 and XSP.XS15 is
i
TT0
-bit position of every outgoing CRC multiframe (under the
EBP
235
a
/S
i
AXS
-bit signaling, remote alarm) is ignored.
XSIF
i
i
-bit positions of the outgoing
-bit of frame 13; RSP.SI2 →
XS13
FALC56 V1.2
XS15
E1 Registers
0
PEB 2256
2002-08-27
(21)
i