mt46h32m16lf Micron Semiconductor Products, mt46h32m16lf Datasheet - Page 80

• Manufacturer Part Number: mt46h32m16lf
• Description: 512mb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Figure 43:
Stopping the External Clock
PDF: 09005aef82ce3074/Source: 09005aef82ce20c9
ddr_mobile_sdram_cmd_op_timing_dia_fr3.08__3.fm - Rev. D 05/08 EN
Command
CKE
CK#
CK
All banks idle with no
activity on the data bus
Deep Power-Down
Notes:
NOP
T0
1. Clock must be stable prior to CKE going HIGH.
2. DPD = deep power-down.
3. Upon exit of deep power-down mode, a full DRAM initialization sequence is required.
One method of controlling the power efficiency in applications is to throttle the clock
that controls the DDR SDRAM. The clock may be controlled in two ways:
• Change the clock frequency
• Stop the clock.
The Mobile DDR SDRAM allows the clock to change frequency during operation only if
all the timing parameters are met and all refresh requirements are satisfied.
The clock can be stopped altogether if there are no DRAM operations in progress that
would be affected by this change. Any DRAM operation already in process must be
completed before entering clock stop mode; this includes the following timings:
t
be complete as defined in the “READs” section on page 49 and the “WRITEs” section on
page 60.
CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the
clock stop mode. One clock cycle and at least one NOP or DESELECT is required after
the clock is restarted before a valid command can be issued. Figure 52 on page 81 illus-
trates the clock stop mode.
RP,
t
RFC,
t
DPD
IS
T1
Enter deep power-down mode
t
2
MRD,
t
WR, and
T2
(
(
(
)
(
)
t
)
(
)
)
(
CKE
(
(
(
)
(
)
)
)
)
t
RPST. In addition, any READ or WRITE burst in progress must
80
Ta0
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ta1
NOP
Exit deep power-down mode
T = 200µs
Ta2
NOP
Mobile DDR SDRAM
©2007 Micron Technology, Inc. All rights reserved
Don’t Care
Operations
Ta3
PRE
3
t
RCD,