mt46h32m16lf Micron Semiconductor Products, mt46h32m16lf Datasheet - Page 27

• Manufacturer Part Number: mt46h32m16lf
• Description: 512mb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Functional Description
PDF: 09005aef82ce3074/Source: 09005aef82ce20c9
ddr_mobile_sdram_cmd_op_timing_dia_fr3.08__3.fm - Rev. D 05/08 EN
The Mobile DDR SDRAM uses a double data rate architecture to achieve high-speed
operation. The double data rate architecture is essentially a 2n-prefetch architecture,
with an interface designed to transfer two data words per clock cycle at the I/O. Single
read or write access for Mobile DDR SDRAM consists of a single 2n-bit-wide, one-clock-
cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-
half-clock-cycle data transfers at the I/O.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the Mobile DDR SDRAM
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. The x16 device has two data
strobes, one for the lower byte and one for the upper byte; the x32 device has four data
strobes, one per byte.
The Mobile DDR SDRAM operates from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at
a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The address bits registered coin-
cident with the ACTIVE command are used to select the bank and row to be accessed.
The address bits registered coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
The Mobile DDR SDRAM provides for programmable READ or WRITE burst lengths of 2,
4, 8, or 16. An auto precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard DDR SDRAMs, the pipelined, multibank architecture of Mobile DDR
SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by
hiding row precharge and activation time.
An auto refresh mode is provided, along with a power saving power-down mode. Deep
power-down mode is offered to achieve maximum power reduction by eliminating the
power of the memory array. Data will not be retained after the device enters deep power-
down mode.
Two self refresh features, temperature-compensated self refresh (TCSR) and partial-
array self refresh (PASR), offer additional power savings. TCSR is controlled by the auto-
matic on-chip temperature sensor. The PASR can be customized using the extended
mode register settings. The two features may be combined to achieve even greater power
savings.
The DLL that is typically used on standard DDR devices is not necessary on the Mobile
DDR SDRAM. It has been omitted to save power.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Functional Description
Mobile DDR SDRAM
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