mt46h32m16lf Micron Semiconductor Products, mt46h32m16lf Datasheet - Page 22

• Manufacturer Part Number: mt46h32m16lf
• Description: 512mb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Table 8:
PDF: 09005aef82d5d305/Source: 09005aef82d5d2e7
512mb_ddr_mobile_sdram_t47m_density__2.fm - Rev. D 05/08 EN
Parameter
SRR-to-READ
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE-to-READ command
delay
Exit power-down mode to first valid
command
Exit SELF REFRESH to first valid
command
Electrical Characteristics and Recommended AC Operating Conditions (continued)
Notes: 1–9 apply to all parameters in this table; V
Notes:
10. Clock frequency is allowed to change only during a clock stop, power-down, or self refresh
11.
1. All voltages referenced to V
2. All parameters assume proper device initialization.
3. Tests for AC timing and electrical AC and DC characteristics may be conducted at nominal
4. The circuit shown below represents the timing reference load used in defining the relevant
5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point at
6. A CK and CK# input slew rate ≥1 V/ns (2 V/ns if measured differentially) is assumed for all
7. All AC timings assume an input slew rate of 1 V/ns.
8. CAS latency definition: with CL = 2, the first data element is valid at (
9. Timing tests may use a V
supply voltage levels, but the related specifications and device operation are guaranteed
for the full voltage ranges specified.
timing parameters of the device. It is not intended to be either a precise representation of
the typical system environment or a depiction of the actual load presented by a production
tester. System designers will use IBIS or other simulation tools to correlate the timing refer-
ence load to system environment. Specifications are correlated to production test condi-
tions (generally a coaxial transmission line terminated at the tester electronics). For the
half-strength driver with a nominal 10pF load, parameters
in the same range. However, these parameters are not subject to production test but are
estimated by design/characterization. Use of IBIS or other simulation tools for system design
validation is suggested.
which CK and CK# cross; the input reference voltage level for signals other than CK/CK# is
V
parameters.
clock at which the READ command was registered; for CL = 3, the first data element is valid
at (2 ×
ing is still referenced to V
erence voltage level is V
mode.
t
higher integer.
DAL = (
I/O
DD
Q/2.
Symbol
t
Full-drive strength
t
WPRES
t
WPRE
t
WPST
t
t
t
WTR
t
SRR
XSR
WR
XP
t
CK +
t
WR/
50
t
t
CK) + (
AC) after the first clock at which the READ command was registered.
0.25
120
0.4
15
M
2
0
2
2
-5
t
RP/
20pF
Max
0.6
t
DD
–
–
–
–
–
–
–
IL
CK): for each term, if not already an integer, round to the next
DD
-to-V
Q/2.
SS
Q/2 or to the crossing point for CK/CK#. The output timing ref-
22
.
I/O
IH
Min
0.25
120
0.4
DD
15
2
0
2
2
swing of up to 1.5V in the test environment, but input tim-
Half-drive strength
/V
-54
DDQ
Max
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0.6
512Mb: x16, x32 Mobile DDR SDRAM
50
–
–
–
–
–
–
–
= 1.70–1.95V
Min
0.25
120
0.4
15
2
0
2
1
10pF
-6
Max
0.6
–
–
–
–
–
–
–
Electrical Specifications
t
AC and
Min
0.25
120
0.4
15
©2004 Micron Technology, Inc. All rights reserved
2
0
1
1
-75
t
QH are expected to be
t
CK +
Max
0.6
–
–
–
–
–
–
–
t
AC) after the
Unit
t
t
t
t
t
CK
CK
ns
CK
ns
CK
CK
ns
Notes
22, 23
24
25
26