mt46h32m16lf Micron Semiconductor Products, mt46h32m16lf Datasheet - Page 10

• Manufacturer Part Number: mt46h32m16lf
• Description: 512mb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Table 1:
PDF: 09005aef82d5d305/Source: 09005aef82d5d2e7
512mb_ddr_mobile_sdram_t47m_density__2.fm - Rev. D 05/08 EN
A8, B7, B8, C7, C8,
D7, D8, E7, E3, D2,
D3, C2, C3, B2, B3,
J8, J9, K7, K8, K2,
K3, J1, J2, J3, H1,
60-Ball VFBGA
G9, G8, G7
J7, H2, H3
G2, G3
H8, H9
F2, F8
G1
H7
A2
VFBGA Ball Descriptions
B8, C7, C8, D7, D8,
R8, P7, P8, N7, N8,
E7, E3, D2, D3, C2,
P2, P3, R2, A8, B7,
J8, J9, K7, K9, K1,
K3, J1, J2, J3, H1,
M2, M3, N2, N3,
90-Ball VFBGA
M7, M8, L7, L3,
C3, B2, B3, A2
K8, K2, F8, F2
G9, G8, G7
J7, H2, H3
H8, H9
G2, G3
G1
H7
RAS#, CAS#,
UDM, LDM
DQ0–DQ15
DQ0–DQ31
DM0–DM3
BA0, BA1
Symbol
(60-ball)
(90-ball)
(60-ball)
(90-ball)
(60-ball)
(90-ball)
CK, CK#
A0–A12
A0–A12
WE#
CKE
CS#
Input
Input
Input
Input
Input
Input
Input
Type
I/O
10
Clock: CK is the system clock input. CK and CK# are
differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge
of CK and the negative edge of CK#. Input and output
data is referenced to the crossing of CK and CK# (both
directions of the crossing).
Clock enable: CKE HIGH activates, and CKE LOW
deactivates, the internal clock signals, input buffers, and
output drivers. Taking CKE LOW enables PRECHARGE
power-down and SELF REFRESH operations (all banks
idle), or ACTIVE power-down (row active in any bank).
CKE is synchronous for all functions except SELF REFRESH
exit. All input buffers (except CKE) are disabled during
power-down and self refresh modes.
Chip select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands
are masked when CS# is registered HIGH. CS# provides
for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#)
define the command being entered.
Input data mask: DM is an input mask signal for write
data. Input data is masked when DM is sampled HIGH
along with that input data during a WRITE access. DM is
sampled on both edges of DQS. Although DM balls are
input-only, the DM loading is designed to match that of
DQ and DQS balls.
Bank address inputs: BA0 and BA1 define the bank to
which an ACTIVE, READ, WRITE, or PRECHARGE
command is being applied. BA0 and BA1 also determine
which mode register is loaded during a LOAD MODE
REGISTER command.
Address inputs: Provide the row address for ACTIVE
commands, and the column address and auto-precharge
bit (A10) for READ or WRITE commands, to select one
location out of the memory array in the respective bank.
During a PRECHARGE command, A10 determines
whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0 and BA1) or all banks (A10 HIGH).
The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
Data input/output: Data bus for x16 and x32.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x16, x32 Mobile DDR SDRAM
Ball Assignments and Descriptions
Description
©2004 Micron Technology, Inc. All rights reserved