mt46h32m16lf Micron Semiconductor Products, mt46h32m16lf Datasheet - Page 76

• Manufacturer Part Number: mt46h32m16lf
• Description: 512mb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

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Figure 39:
PDF: 09005aef82ce3074/Source: 09005aef82ce20c9
ddr_mobile_sdram_cmd_op_timing_dia_fr3.08__3.fm - Rev. D 05/08 EN
Command
BA0, BA1
Address
DQS
DM
CKE
DQ
CK#
A10
CK
5
5
1
5
Auto Refresh Mode
t
t
IS
IS
NOP 2
T0
t
Notes:
IH
t
IH
Bank(s)
One bank
All banks
Auto refresh mode is used during normal operation of the Mobile DDR SDRAM and is
analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs. The AUTO
REFRESH command is nonpersistent and must be issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command.
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. The auto refresh period begins when
the AUTO REFRESH command is registered and ends
PRE
1. PRE = PRECHARGE; AR = AUTO REFRESH.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at
3. NOP or COMMAND INHIBIT are the only commands allowed until after
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-to-
Although it is not a JEDEC requirement, CKE must be active (HIGH) during the auto
refresh period to allow for future functional features. The auto refresh period begins
when the AUTO REFRESH command is registered and ends
T1
4
t
these times. CKE must be active during clock positive transitions.
be active during clock positive transitions.
(for example, must precharge all active banks).
back AUTO REFRESH commands.
CK
NOP
Valid
T2
2
t
CH
t
RP
t
CL
NOP
T3
2
T4
AR
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RFC
NOP
T a 0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2, 3
T a 1
AR
6
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RFC later.
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NOP
Valid
Tb0
t
2, 3
RFC later.
Mobile DDR SDRAM
©2007 Micron Technology, Inc. All rights reserved
t
RFC
NOP 2
Tb1
6
t
RFC time; CKE must
Operations
Don’t Care
ACTIVE
Tb2
Bank
Row
Row