mt46h32m16lf Micron Semiconductor Products, mt46h32m16lf Datasheet - Page 61

• Manufacturer Part Number: mt46h32m16lf
• Description: 512mb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Figure 23:
PDF: 09005aef82ce3074/Source: 09005aef82ce20c9
ddr_mobile_sdram_cmd_op_timing_dia_fr3.08__3.fm - Rev. D 05/08 EN
Data Input Timing
Notes:
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 41 on page 69 and Figure 42 on page 70. Note that only the data-in pairs
that are registered prior to the
subsequent data-in should be masked with DM, as shown in Figure 41 and Figure 42.
After the PRECHARGE command, a subsequent command to the same bank cannot be
issued until
DQS
1. WRITE command issued at T0.
2.
3.
4. For x16, LDQS controls the lower byte; UDQS controls the upper byte. For x32, DQS0 con-
5. For x16, LDM controls the lower byte; UDM controls the upper byte. For x32, DM0 controls
DM
CK#
DQ
CK
t
t
trols DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls
DQ[31:24].
DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls DQ[31:24].
4
5
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
t
WPRES
T0
t
1
DQSS
t
RP is met.
t DS
T1
D
b
IN
t
WPRE
t
DSH
t DH
T1n
2
Transitioning Data
t
61
t
DQSL
DSS
t
WR period are written to the internal array, and any
3
T2
t
t
t
DQSH
DSH
t
DQSS (MAX).
DQSS (MIN).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2n
2
t
t
WPST
DSS
3
T3
Don’t Care
Mobile DDR SDRAM
©2007 Micron Technology, Inc. All rights reserved
Operations