mt46h32m16lf Micron Semiconductor Products, mt46h32m16lf Datasheet - Page 18

• Manufacturer Part Number: mt46h32m16lf
• Description: 512mb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

Table 6:
PDF: 09005aef82d5d305/Source: 09005aef82d5d2e7
512mb_ddr_mobile_sdram_t47m_density__2.fm - Rev. D 05/08 EN
Parameter/Condition
Operating 1 bank active-precharge current:
t
between valid commands; Address inputs are switching
every 2 clock cycles; Data bus inputs are stable
Precharge power-down standby current: All banks idle;
CKE is LOW; CS is HIGH;
control inputs are switching; Data bus inputs are stable
Precharge power-down standby current: Clock stopped;
All banks idle; CKE is LOW; CS is HIGH, CK = LOW, CK# =
HIGH; Address and control inputs are switching; Data bus
inputs are stable
Precharge nonpower-down standby current: All banks
idle CKE = HIGH; CS = HIGH;
control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current: Clock
stopped; All banks idle, CKE = HIGH; CS = HIGH; CK =
LOW, CK# = HIGH; Address and control inputs are
switching; Data bus inputs are stable
Active power-down standby current: 1 bank active, CKE =
LOW; CS = HIGH;
inputs are switching; Data bus inputs are stable
Active power-down standby current: Clock stopped; 1
bank active, CKE = LOW; CS = HIGH; CK = LOW; CK# =
HIGH; Address and control inputs are switching; Data bus
inputs are stable
Active nonpower-down standby: 1 bank active; CKE =
HIGH; CS = HIGH;
inputs are switching; Data bus inputs are stable
Active nonpower-down standby: Clock stopped; 1 bank
active, CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH;
Address and control inputs are switching; Data bus inputs
are stable
Operating burst read: 1 bank active; BL = 4; CL = 3;
t
Address inputs are switching every 2 clock cycles; 50%
data changing each burst
Operating burst write: One bank active; BL = 4;
(MIN); Continuous WRITE bursts; Address inputs are
switching; 50% data changing each burst
Auto refresh: Burst refresh; CKE = HIGH;
Address and control inputs are switching;
Data bus inputs are stable
Deep power-down current: Address and control pins are
stable; Data bus inputs are stable
RC =
CK =
t
t
RC (MIN);
CK (MIN); Continuous READ bursts; I
I
Notes: 1–5 apply to all parameters/conditions in this table; notes appear on page 19; V
DD
t
CK =
t
t
Specifications and Conditions (x32)
CK =
CK =
t
CK (MIN); CKE is HIGH; CS is HIGH
t
t
CK (MIN); Address and control
t
CK (MIN); Address and control
CK =
t
CK =
t
CK (MIN); Address and
t
CK (MIN); Address and
OUT
t
t
RFC
RFC =
= 0mA;
t
CK =
= 110ns
t
REFI
t
CK
Symbol
18
I
I
I
I
I
I
I
I
I
DD
DD
I
DD
I
DD
DD
DD
DD
DD
DD
I
DD
DD
I
I
DD
DD
DD
2NS
3NS
2PS
3PS
4W
2N
3N
5A
3P
4R
2P
0
5
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x16, x32 Mobile DDR SDRAM
300
300
125
125
105
70
15
15
-5
8
3
2
8
3
300
300
120
120
105
-54
65
15
15
8
3
2
8
3
Max
10
Electrical Specifications
300
300
115
115
100
60
15
15
-6
8
3
2
8
3
©2004 Micron Technology, Inc. All rights reserved
300
300
100
100
100
-75
50
12
15
DD
8
3
2
8
3
/V
DD
Q = 1.70–1.95V
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
Notes
10, 11
7, 13
7, 8
10
6
7
9
9
8
6
6
6
6