mt46h32m16lf Micron Semiconductor Products, mt46h32m16lf Datasheet - Page 23

• Manufacturer Part Number: mt46h32m16lf
• Description: 512mb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef82d5d305/Source: 09005aef82d5d2e7
512mb_ddr_mobile_sdram_t47m_density__2.fm - Rev. D 05/08 EN
12. Referenced to each output group: for x16, LDQS with DQ0–DQ7; and UDQS with DQ8–
13. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/
14. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and
15. These parameters guarantee device timing but are not tested on each device.
16. The valid data window is derived by achieving other specifications:
17.
18.
19.
20. Fast command/address input slew rate
21. The refresh period equals 64ms. This equates to an average refresh rate of 7.8125µs.
22. This is not a device limit. The device will operate with a negative value, but system perfor-
23. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The
24. The maximum limit for this parameter is not a device limit. The device will operate with a
25. At least one clock cycle is required during
26. Clock must be toggled a minimum of two times during the
DQ15. For x32, DQS0 with DQ0–DQ7; DQS1 with DQ8–DQ15; DQS2 with DQ16–DQ23; and
DQS3 with DQ24–DQ31.
DM/DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to
and
is uncertain.
addresses) are measured between V
V
t
cycle and a practical data valid window can be derived. The clock is allowed a maximum duty
cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio.
t
inputs, collectively.
t
These parameters are not referenced to a specific voltage level, but specify when the device
output is no longer driving (
t
V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated:
per each 100 mV/ns reduction in slew rate from the 0.5 V/ns.
remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain.
mance could be degraded due to bus turnaround.
case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously
in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this
time, depending on
greater value for this parameter, but system performance (bus turnaround) will degrade
accordingly.
QH (
HP (MIN) is the lesser of
HZ and
HZ (MAX) will prevail over
IL
(
AC
t
DH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality
t
) for falling input signals.
HP -
t
LZ transitions occur in the same access time windows as valid data transitions.
t
QHS). The data valid window derates directly proportional with the clock duty
t
DQSS.
t
CL (MIN) and
t
t
DQSCK (MAX) +
23
HZ) or begins driving (
IL
(
DC
≥
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
512Mb: x16, x32 Mobile DDR SDRAM
CH (MIN) actually applied to the device CK and CK#
1 V/ns. Slow command/address input slew rate
) to V
t
WR time when in auto precharge mode.
t
RPST (MAX) condition.
IH
(
AC
) for rising input signals and V
t
LZ).
Electrical Specifications
t
XSR period.
t
IH has 0ps added, therefore, it
©2004 Micron Technology, Inc. All rights reserved
t
IS has an additional 50ps
t
HP (
t
CK/2),
t
DQSQ, and
IH
(
DC
) to
≥
t
DS
0.5