mt46h32m16lf Micron Semiconductor Products, mt46h32m16lf Datasheet - Page 60

• Manufacturer Part Number: mt46h32m16lf
• Description: 512mb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

WRITEs
PDF: 09005aef82ce3074/Source: 09005aef82ce20c9
ddr_mobile_sdram_cmd_op_timing_dia_fr3.08__3.fm - Rev. D 05/08 EN
WRITE bursts are initiated with a WRITE command, as shown in Figure 11 on page 31.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the WRITE
commands used in the following illustrations, auto precharge is disabled. Basic data
input timing is shown in Figure 31 on page 61 (this timing applies to all WRITE opera-
tions).
Input data appearing on the data bus is written to the memory array subject to the state
of data mask DM inputs coincident with the data. If DM is registered LOW, the corre-
sponding data will be written; if DM is registered HIGH, the corresponding data will be
ignored, and the write will not be executed to that byte/column location. DM operation
is illustrated in Figure 32 on page 62.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble. The write burst
is complete when the write postamble and
The time between the WRITE command and the first corresponding rising edge of DQS
(
clock cycle). All of the WRITE diagrams show the nominal case, and where the two
extreme cases (that is,
also been included. Figure 33 on page 63 shows the nominal case and the extremes of
t
been initiated, the DQs will remain High-Z and any additional input data will be
ignored.
Data for any WRITE burst may be concatenated with or truncated by a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst that is being truncated. The new WRITE command should be issued x cycles after
the first WRITE command, where x equals the number of desired data element pairs
(pairs are required by the 2n-prefetch architecture).
Figure 34 on page 63 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 35 on page 64. Full-speed random write accesses within a
page or pages can be performed, as shown in Figure 36 on page 64.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst,
on page 65.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 38 on page 66. Note that only the data-in pairs that are registered prior to the
t
masked with DM, as shown in Figure 39 on page 67.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst,
Figure 40 on page 68.
DQSS for a burst of 4. Upon completion of a burst, assuming no other commands have
WTR period are written to the internal array, and any subsequent data-in should be
t
DQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one
t
DQSS [MIN] and
60
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t
DQSS [MAX]) might not be intuitive, they have
t
WR or
t
WTR should be met, as shown in Figure 37
t
WTR are satisfied.
t
WR should be met, as shown in
Mobile DDR SDRAM
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Operations