MT28F640J3 Micron Semiconductor Products, MT28F640J3 Datasheet
MT28F640J3
Available stocks
Related parts for MT28F640J3
MT28F640J3 Summary of contents
Page 1
... Commercial Temperature (0ºC to +85ºC) Extended Temperature (-40ºC to +85ºC) 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S ...
Page 2
... V in this Q-Flash family PEN 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 can provide data protection when connected to ground. This pin also enables program or erase lockout during power transition. Micron’s even-sectored Q-Flash devices offer indi- vidual block locking that can lock and unlock a block using the sector lock bits command sequence ...
Page 3
... A23 only exists on the 128Mb device. On the 32Mb and 64Mb, this pin/ball connect (NC). 3. The # symbol indicates signal is active LOW. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to Micron part num- bers in Table 1 ...
Page 4
... Control Logic A0–A22 CE0 CE Logic CE1 Command CE2 Execution OE# Logic WE# RP STS V PEN 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 FUNCTIONAL BLOCK DIAGRAM (128Mb) Addr. Buffer/ Latch Addr. Power (Current) Counter Control State Y - Machine Decoder V PP Switch/ Pump ...
Page 5
... Control Logic A0–A21 CE0 CE Logic CE1 Command CE2 Execution OE# Logic WE# RP STS V PEN 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 FUNCTIONAL BLOCK DIAGRAM (32Mb) Addr. Buffer/ Latch Addr. Power (Current) Counter Control State Y - Machine Decoder V PP Switch/ Pump ...
Page 6
... E1, E3, F3, F4, 45, 47, 50, 52 F5, H5, G7 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 SYMBOL TYPE WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command execution logic (CEL the memory array. ...
Page 7
... H3, A6 21, 42, 48 B2, H4 – B6, C6, D5, D6, E6, F6, F7, H2 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 SYMBOL TYPE V Q Supply V Q controls the output voltages. To obtain output CC CC voltage compatible with system data bus voltages, connect the system supply voltage. ...
Page 8
... In this state, data is internally read and stored in a 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 127 NOTE: For single-chip applications, CE2 and CE1 can be 63 high-speed page buffer. A0– ...
Page 9
... WE# or the first edge of CEx that disables the device (see Table 2). Standard microprocessor write timings are used. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Device Identifier Code Memory Map ), and IH 7FFFFFh 7F0003h ...
Page 10
... See Read Query Mode Command section for read query data. 10. Command writes involving block erase, program, or lock bit configuration are reliably executed when within specification. CC 11. Refer to Table 4 for valid D 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 3 Bus Operations CE0, CE1 ...
Page 11
... SCS CLEAR BLOCK SCS LOCK BITS PROTECTION PROGRAM *Notes appear on the next page. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 , only READ FIGURATION operations. Device operations are se- PPLK lected by writing specific commands into the CEL en- seen in Table 4. ...
Page 12
... Program suspend can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is initiated. 15. The CLEAR BLOCK LOCK BITS operation simultaneously clears all block lock bits. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 128Mb, 64Mb, 32Mb Q-FLASH MEMORY will fail. ...
Page 13
... Therefore, word addressing where these lower addresses are not toggled by the system is “Not Applicable” for x8-configured devices. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 QUERY STRUCTURE OUTPUT The query “data base” enables system software to obtain information about controlling the Flash compo- nent. The device’ ...
Page 14
... BA = Block address beginning location (i.e., 020000h is block two’s beginning location when the block size is 64K-word). 3. Offset 15 defines “P,” which points to the Primary Extended Query Table. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 6 VALUE OFFSET A7– ...
Page 15
... Secondary algorithm extended query table address; 0000h means none exists 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 tionally, it indicates the specification version and sup- ported vendor-specified command set(s). Table 8 Block Status Register Table 9 CFI Identification 15 Micron Technology, Inc ...
Page 16
... Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 10 System Interface Information n µs 16 128Mb, 64Mb, 32Mb Q-FLASH MEMORY ADDRESS ...
Page 17
... Erase Block Region 1 Information Bits 0– number of identical-size erase blocks Bits 16– region erase block(s) size are z x 256 bytes 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 11a Device Geometry Definitions n in number of bytes n Table 11b ...
Page 18
... Bits 4–7 Hex value in volts NOTE: 1. Future devices may not support the described “Legacy Lock/Unlock” function. On these devices, bit 3 would have a value of “0.” 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 128Mb, 64Mb, 32Mb Q-FLASH MEMORY Table 12 ADDRESS ...
Page 19
... Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. (P+15)h Reserved for future use. NOTE: 1. The variable “P” pointer which is defined at CFI offset 15h. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 13 Protection Register Information n = factory preprogrammed bytes n ...
Page 20
... X selects the specific block’s lock configuration code. See Figure 2 for the device identifier code memory map. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 erasure, or lock bit configuration. After writing this com- mand, all subsequent READ operations output data from the status register until another valid command is written ...
Page 21
... SR2 = PROGRAM SUSPEND STATUS (PSS Program Suspended 0 = Program in Progress/Completed Yes SR1 = DEVICE PROTECT STATUS (DPS Block Lock Bit Detected, Operation Aborted 0 = Unlock Yes SR0 = RESERVED FOR FUTURE ENHANCEMENTS 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 16 Status Register Definitions ECLBS PSLBS V PENS ...
Page 22
... This two-step setup command sequence ensures that block contents are not acciden- tally erased. An invalid block erase command sequence 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 17 RESERVED 6–0 results in status register bits SR4 and SR5 being set to “ ...
Page 23
... For additional BUFFER WRITEs, issue another WRITE- to-BUFFER SETUP command and check XSR7. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/ error occurs during a WRITE, the device stops writing, and status register bit SR4 is set to a “1” to indicate a program failure. The ISM only detects errors for “ ...
Page 24
... CONFIGURATION command. The devices default to the asynchronous page mode. If this command is given, the operation of the device will not be affected. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 READ CONFIGURATION Micron’s Q-Flash devices support both asynchro- nous page mode and standard word/byte READs with- out configuration requirement ...
Page 25
... An invalid SET BLOCK LOCK BITS command results in status register bits SR4 and SR5 being set to “1.” Also, reliable operation occurs only when V 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table 18 Configuration Coding Definitions DQ5 DQ4 ...
Page 26
... The allowable addresses are shown in Table 19 and Table 20. Any attempt to address PRO- TECTION PROGRAM commands outside the defined 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ protection register address space results in a status PEN PENLK register error (program error bit SR4 is set to “ ...
Page 27
... User C User D User E User F User NOTE: 1. All address lines not specified in the above tables must be “0” when accessing the protection register (i.e., A22–A9 = 0). 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Table ...
Page 28
... The status register indicates an “improper command sequence” if the WRITE-to-BUFFER command is aborted. Follow this with a CLEAR STATUS REGISTER command. 7. Toggling OE# (LOW to HIGH to LOW) updates the status register. This can be done in place of issuing the READ STATUS REGISTER command. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE READ ...
Page 29
... SR1 = Device Protect Error 0 1 Programming Error SR4 = 0 Byte/Word Program Successful 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 128Mb, 64Mb, 32Mb Q-FLASH MEMORY BUS OPERATION COMMAND COMMENTS WRITE SETUP BYTE/ Data = 40h WORD Addr = Location to be PROGRAM WRITE ...
Page 30
... SR2 = 1 Write FFh Read Data Array 1 No Done Reading Yes Write D0h Programming Resumed 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE READ STANDBY STANDBY WRITE Programming READ Completed WRITE Write FFh Read Data Array ...
Page 31
... Read Status Register No SR7 = Suspend Erase 1 Full Status Check if Desired Erase Flash Block(s) Complete 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE WRITE READ STANDBY Suspend No Erase Loop The erase confirm byte must follow erase setup. ...
Page 32
... Program Program? Read Array Program No Data Loop Done? Yes Write D0h BLOCK ERASE Resumed 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE READ STANDBY STANDBY WRITE BLOCK ERASE Completed Write FFh Read Data Array 32 128Mb, 64Mb, 32Mb ...
Page 33
... SET BLOCK LOCK BITS SR4 = 0 SET BLOCK LOCK BITS Successful 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE WRITE READ STANDBY Repeat for subsequent lock bit operations. Full status check can be done after each lock bit set ...
Page 34
... SR4 CLEAR BLOCK LOCK SR5 = 0 CLEAR BLOCK LOCK BITS Successful 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE WRITE READ STANDBY Write FFh after the CLEAR BLOCK LOCK BITS operation to place device in read array mode. ...
Page 35
... PROGRAMMING Error Attempted Program SR1, SR4 = Locked Register – PROGRAM Successful 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 BUS OPERATION COMMAND WRITE WRITE READ STANDBY PROTECTION PROGRAM operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error ...
Page 36
... High-Z when the ISM has finished executing the internal algorithm. See the CONFIGURATION com- 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 mand for alternate configurations of the STS pin. STS can be connected to an interrupt input of the system CPU or controller. STS is active at all times. In default ...
Page 37
... The CEL latches commands issued by system software and is not altered by V transitions, or ISM actions. Its state is read array mode 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 upon power-up, upon exiting reset/power-down mode, or after V kept at or above V ...
Page 38
... Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 128Mb, 64Mb, 32Mb Q-FLASH MEMORY operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
Page 39
... NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). 2. Sampled, not 100% tested. 3. Includes STS. 4. MT28F320J3RG-11 F and MT28F640J3RG-12 F only. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ T ...
Page 40
... Typically connected to V PEN 8. Block erase, programming, and lock bit configurations are inhibited when V the range between V (MIN) and V LKO 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ CONDITIONS = V (MAX Device is enabled; ...
Page 41
... Typically connected to V PEN 8. Block erase, programming, and lock bit configurations are inhibited when V the range between V (MIN) and V LKO 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ CONDITIONS CMOS inputs PEN CC ...
Page 42
... CC Input V 0.0 NOTE: AC test inputs are driven (50 Q). Input rise and fall times (10% to 90%) < 5ns. CC Transient Equivalent Testing Load Circuit 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 Figure 2.7V–3.6V Q/2 Test Points CC Q for a logic 1 and 0.0V for a logic 0. Input timing begins, and output timing ends ...
Page 43
... See Figures 12 and 13, Transient Input/Output Reference Waveform for V Transient Equivalent Testing Load Circuit for testing characteristics. 5. When reading the Flash array, a faster DEVICE IDENTIFIER READs. 6. Sampled, not 100% tested. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ SYMBOL t RC ...
Page 44
... RWH (32Mb) NOTE: CEx LOW is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEx HIGH is defined as the first edge of CE0, CE1, or CE2 that disables the device. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/ VALID VALID ...
Page 45
... AA is required in addition to 9. STS timings are based on STS configured in its RY/BY# default mode. 10. V should be held at V PEN PENH 0). 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ WPH ( and D for block erase, program, or lock bit configuration. IN ...
Page 46
... These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. Effective per-byte program time is 4.7µs/byte (typical). 7. Effective per-word program time is 9.4µs/word (typical). 8. MAX values are measured at worst-case temperature and V 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ SYMBOL t ...
Page 47
... Write block erase, write buffer, or program setup. 4. Write block erase or write buffer confirm, or valid address and data. 5. Automated erase delay. 6. Read status register or query data. 7. WRITE READ ARRAY command. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 WRITE OPERATIONS Note 3 Note 4 Note 5 A ...
Page 48
... CE0, CE1, or CE2 that disables the device (see Table 2). STS is shown in its default mode (RY/BY#). 2. Erase resume, or program resume. 3. Read status, erase suspend or program suspend. 4. STS value will be: V after ERASE SUSPEND and PROGRAM SUSPEND commands IH V after READ STATUS command IL 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 RESUME OPERATIONS Note ...
Page 49
... RP# pulse LOW time is 100ns reset time, PHQV, is required from the latter of STS (in RY/BY# mode) or RP# going HIGH until outputs are valid. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 ≤ +85ºC), Extended Temperature (-40ºC ≤ SYMBOL t PLPH ...
Page 50
... PIN #1 INDEX +0.03 0.15 -0.02 NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 56-PIN TSOP TYPE I 20.00 ±0.10 18.40 ±0.08 14.00 ±0.08 SEE DETAIL A 1.20 MAX 50 128Mb, 64Mb, 32Mb ...
Page 51
... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the Micron and M logos and Q-Flash are trademarks and/or servicemarks of Micron Technology, Inc. 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/02 64-BALL FBGA 7.00 BALL A1 ID BALL A1 1 ...
Page 52
... Removed Block Erase Status bit Rev. 3 ......................................................................................................................................................................................... 6/01 • Updated package drawing and corresponding notes Rev. 2 ......................................................................................................................................................................................... 5/01 • Added 128Mb device information • Added 64-ball FBGA (1.0mm pitch) package Original document, Rev. 1 .................................................................................................................................................. 12/00 128Mb, 64Mb, 32Mb Q-Flash Memory MT28F640J3_7.p65 – Rev. 6, Pub. 8/ APA ...