mt46h32m16lf Micron Semiconductor Products, mt46h32m16lf Datasheet - Page 71

• Manufacturer Part Number: mt46h32m16lf
• Description: 512mb X16, X32 Mobile Ddr Sdram
• Manufacturer: Micron Semiconductor Products

PRECHARGE
Auto Precharge
Concurrent Auto Precharge
PDF: 09005aef82ce3074/Source: 09005aef82ce20c9
ddr_mobile_sdram_cmd_op_timing_dia_fr3.08__3.fm - Rev. D 05/08 EN
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access
some specified time (
mines whether one or all banks are to be precharged, and in the case where only one
bank is to be precharged (A10 = LOW), inputs BA0 and BA1 select the bank. When all
banks are to be precharged (A10 = HIGH), inputs BA0 and BA1 are treated as a “Don’t
Care.” After a bank has been precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that bank. A PRECHARGE command
will be treated as a NOP if there is no open row in that bank (idle state), or if the previ-
ously open row is already in the process of precharging.
Auto precharge is a feature that performs the same individual-bank precharge function
described previously, but without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is nonpersistent in that it is either enabled or disabled for each indi-
vidual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating
each burst type in “Operations” on page 34. The READ with auto precharge enabled or
WRITE with auto precharge enabled states can each be broken into two parts: the access
period and the precharge period. The access period starts with registration of the
command and ends where the precharge period (or
precharge, the precharge period is defined as if the same burst was executed with auto
precharge disabled and then followed with the earliest possible PRECHARGE command
that still accesses all the data in the burst. For WRITE with auto precharge, the precharge
period begins when
addition, during a WRITE with auto precharge, at least one clock is required during
time. During the precharge period, the user must not issue another command to the
same bank until
Bank READ operations with and without auto precharge are shown in Figure 43 on
page 72 and Figure 44 on page 73. Bank WRITE operations with and without auto
precharge are shown in Figure 45 on page 74 and Figure 46 on page 75.
This device supports concurrent auto precharge such that when a READ with auto
precharge enabled or a WRITE with auto precharge is enabled any command to another
bank is allowed, as long as that command does not interrupt the read or write data
transfer already in process. This feature allows the precharge to complete in the bank in
which the READ or WRITE with auto precharge was executed, without an explicit
PRECHARGE command being required, thus freeing the command bus for operations in
other banks. During the access period of a READ or WRITE with auto precharge, only
ACTIVE and PRECHARGE commands may be applied to other banks. During the
precharge period, ACTIVE, PRECHARGE, READ, and WRITE commands may be applied
to other banks. In either situation, all other related limitations apply (for example,
contention between READ data and WRITE data must be avoided).
t
RP is satisfied.
t
WR ends, with
t
RP) after the PRECHARGE command is issued. Input A10 deter-
71
t
WR measured as if auto precharge was disabled. In
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP) begins. For READ with auto
t
RAS (MIN), as described for
Mobile DDR SDRAM
©2007 Micron Technology, Inc. All rights reserved
Operations
t
WR