LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 93

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
sysIO Standards Supported in Each Bank
Table 7-3. I/O Standards Supported by Various Banks
LVCMOS Buffer Configurations
All LVCMOS buffers have programmable pull, programmable drive and programmable slew configurations that can
be set in the software.
Programmable Pull-up/Pull-Down/Buskeeper
When configured as LVCMOS or LVTTL, each sysIO buffer has a weak pull-up, a weak pull-down resistor and a
weak buskeeper (bus hold latch) available. Each I/O can independently be configured to have one of these features
or none of them.
Programmable Drive
Each LVCMOS or LVTTL output buffer pin has a programmable drive strength option. This option can be set for
each I/O independently. The drive strength setting available are 2mA, 4mA, 6mA, 8mA, 12mA, 16mA and 20mA.
Types of I/O Buffers
Output Standards
Supported
Inputs
Clock Inputs
PCI Support
LVDS Output Buffers
1. These differential standards are implemented by using complementary LVCMOS driver with external resistor pack.
2. This mode uses LVDS25E mode with alternative resistor pack values.
Description
Single-ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I, III
HSTL18_I, II, III
SSTL18D Class I,
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I, III,
HSTL18D Class I, III
PCI33
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 with clamp
1, 2
Banks 0-1
1
Top Side
1
1
Single-ended and
Differential
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL25 Class I, II
SSTL33 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I,
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I, III
HSTL18D Class I, III
PCI33
LVDS
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 no clamp
LVDS (3.5mA) Buffers
1, 2
Right Side
Banks 2-3
1
1
1
7-5
Single-ended
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I
SSTL25D Class I, II
SSTL33D Class I, II
HSTL15D Class I, III
HSTL18D Class I, III
PCI33
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
PCI33 with clamp
LatticeECP/EC sysIO Usage Guide
Bottom Side
1, 2
Banks 4-5
1
1
1
Single-ended and
PCI no clamp
Differential
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I, III
HSTL18 Class I, II, III
SSTL18D Class I,
SSTL25D Class I, II
SSTL33D_I, II
HSTL15D Class I, III
HSTL18D Class I, III
PCI33
LVDS
LVDS25E
LVPECL
BLVDS
RSDS
All Single-ended,
Differential
All Single-ended,
Differential
LVDS (3.5mA) Buffers
1, 2
Banks 6-7
1
Left Side
1
1