LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 134

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
--Module instantiation
U9: DQSDLL
Verilog Usage
// Attribute Assignment
defparam U9.DEL_VAL = “10”,
//Module instantiation
DQSDLL U9 (.CLK (CLK), .UDDCNTL(UDDCNTL), .RST(RESET), .DQSDEL(dqsdel),
DQSBUF
This primitive implements the DQS Delay and the DQS transition detector logic. Figure 9-5 shows the DQSBUFB
function. The preamble detect signal is also generated within this primitive.
Figure 9-5. DQSBUFB Function
Figure 9-6 shows the primitive symbol and its ports.
Figure 9-6. DQSBUFB Symbol
Table 9-3 provides a description of the I/O ports associated with the DQSBUFB primitive.
PORT MAP( CLK
U9.DEL_ADJ = “PLUS”,
U9.LOCK_SENSITIVITY = “HIGH”;
.LOCK(DLL_LOCK));
READ
DQSI
CLK
UDDCNTL =>
RST
DQSDEL
LOCK
V
(DV ~ 170mV)
REF
V
=>
=>
=>
=>
REF
- DV
CLK,
UDDCNTL,
RESET,
dqsdel,
DLL_LOCK);
+
-
+
-
PRMBDET
DQSI
CLK
READ
DQSDEL
DQSBUFB
DQSBUFB
9-5
DDRCLKPOL
PRMBDET
TRANSITION
DQSO
DQSC
DQSDEL
DETECT
DQS
DQSDEL
Lattice ECP/EC DDR Usage Guide
DQSO
DDRCLKPOL