LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 228

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Lattice ECP/EC sysCONFIG Usage Guide
Synchronous to External DONE Signal
The DONE Pin can be selected to delay wake up. If DONE_EX is true, then the wake-up sequence will be delayed
until the DONE pin is driven high externally, then the device will follow the selected wake-up sequence.
Wake-up Clock Selection
The wake-up sequence is synchronized to a clock source, the user shall select the clock source to wake up to. The
clock sources are CCLK, TCK and User Clock. The default shall be either TCK or CCLK depending on the pro-
gramming/configuration method. The default clock should be TCK if using ispJTAG and CCLK if using sysCONFIG.
The User Clock is chosen at the time of design. The user can select any of the CLK pins of the device or a net
(routing node) as the User Clock source. Some sources use BCLK to represent the user clock. The WAKEUP_CLK
shall default to CCLK or TCK.
Wake On PLL Lock
If selected, the LatticeECP/EC device will wait for a lock signal from the PLL before the wake-up sequence begins.
The Wake On lock option must be set by the Wake_on_lock preference.
Read Back
Read back of the configuration memory through sysCONFIG can be done in two different ways. One is transparent
and the device remains alive and functioning. The other shuts the device down and reads the configuration mem-
ory back.
Read Sequence
To read the configuration memory data or register contents back, WRITEN is first set to low to send the read
instruction into the device. The device will read in the command from the host and execute the command once read
in. If the LatticeECP/EC device cannot have the data ready by the next clock cycle, it will drive the BUSY pin high.
When BUSY is high, the device will continue to execute the command regardless of the state of the CSN or CS1N
pins. The device will drive the BUSY pin low when the data is ready but will not drive the D[0:7] until the CSN and
CS1N pin is pulled low by the host. The WRITEN pin should be pulled high after sending in the command. The
CSN, CS1N and WRITEN signals are latched and the device will switch to read mode on the rising edge of CCLK.
If the LatticeECP/EC device needs more than one clock cycle to switch the bus around, BUSY will be kept high until
the D[0:7] is ready.
As in the Write sequence, CSN and CS1N signals can be used to temporarily pause the read sequence in case the
host system is busy. The data is read at the next rising CCLK edge, after CSN and CS1N pins are set to low and
the BUSY pin is low.
Transparent Read Back
Using the Slave Parallel Mode for read back, the user I/Os will remain functional. The Slave Parallel port pins must
be retained in order to allow read back by setting the PERSISTENCE preference to ON. CCLK becomes input only.
Configuration Mode Read Back
Read back can also be done with the LatticeECP/EC device in configuration mode. Only the Slave Parallel Mode is
supported for configuration read back. By driving the WRITEN pin high, the Slave Parallel port will watch for the
read back request from the host device.
Software Control
In order to control the configuration of the LatticeECP/EC device beyond the default settings, software preferences
can be used. Table 13-4 is a list of the preference, the default settings and the section more information about the
preference can be found.
13-14