LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 131

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 9-1. Typical DDR Interface
Figure 9-2. DQ-DQS During READ
Figure 9-3. DQ-DQS During WRITE
Implementing DDR Memory Interfaces with the LatticeECP/EC Devices
This section describes how to implement the read and write sections of a DDR memory interface. It also provides
details of the DQ and DQS grouping rules associated with the LatticeECP/EC devices.
DQ-DQS Grouping
When interfacing to the DDR SDRAM memory, the designer needs to use the dedicated DQ-DQS groups available
on the device. For the LatticeECP/EC devices, there is one dedicated DQS pin for every 16 I/Os. Any eight of these
I/O can be used to assign the DQ data pins. The ninth I/O of this group of 16 I/Os is the dedicated DQS pin. When
not interfacing with the memory these pins can be used as general purpose I/Os. Each of these dedicated DQS
(at PIN)
(at PIN)
DQS
DQ
(DDR Memory
(at REG)
(at REG)
(at PIN)
(at PIN)
Controller)
DQS
DQS
DQ
DQ
FPGA
COMMAND
CONTROL
CLK/CLKN
ADDRESS
DQ<7:0>
DQS
DM
Preamble
REG and 90
DQS PIN to
Phase Shift
COMMAND
CONTROL
CLK/CLKN
ADDRESS
Degree
DQ<7:0>
DQS
DM
9-2
8
X
Y
Z
Lattice ECP/EC DDR Usage Guide
Postamble
DQ<7:0>
DQS
DM
ADDRESS
COMMAND
CONTROL
CLK/CLKN
DDR Memory