LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 5

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
LatticeECP/EC DDR Usage Guide
LatticeECP/EC sysCLOCK PLL Design and Usage Guide
Initializing Memory ........................................................................................................................................... 8-20
Technical Support Assistance.......................................................................................................................... 8-21
Appendix A. Attribute Definitions...................................................................................................................... 8-22
Introduction ........................................................................................................................................................ 9-1
Generic DDR Implementation ............................................................................................................................ 9-1
DDR SDRAM Interfaces Overview..................................................................................................................... 9-1
Implementing DDR Memory Interfaces with the LatticeECP/EC Devices.......................................................... 9-2
Technical Support Assistance.......................................................................................................................... 9-17
Appendix A. Verilog Example of DDR Input and Output Modules ................................................................... 9-18
Appendix B. VHDL Example of a DDR Memory Interface Using
Appendix C. List of Compatible DDR SDRAM ................................................................................................. 9-27
Introduction ...................................................................................................................................................... 10-1
Features ........................................................................................................................................................... 10-1
Functional Description...................................................................................................................................... 10-1
LatticeECP/EC PLL Primitive Definitions ......................................................................................................... 10-3
Equations for Generating Input and Output Frequency Ranges ...................................................................... 10-7
PLL Usage in Module Manager and HDL ........................................................................................................ 10-8
LatticeECP/EC Devices .............................................................................................................................. 9-21
True Dual Port RAM (RAM_DP_TRUE) – EBR Based ............................................................................. 8-7
Pseudo Dual Port RAM (RAM_DP) – EBR-Based.................................................................................... 8-9
Read Only Memory (ROM) – EBR Based............................................................................................... 8-12
First In First Out (FIFO, FIFO_DC) – EBR Based................................................................................... 8-13
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based.......................................................... 8-16
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based ............................................................ 8-17
Distributed ROM (Distributed_ROM) – PFU Based ................................................................................ 8-19
Initialization File Format .......................................................................................................................... 8-20
DATA_WIDTH......................................................................................................................................... 8-22
REGMODE.............................................................................................................................................. 8-22
RESETMODE ......................................................................................................................................... 8-22
CSDECODE............................................................................................................................................ 8-22
WRITEMODE.......................................................................................................................................... 8-22
GSR ........................................................................................................................................................ 8-22
DQ-DQS Grouping .................................................................................................................................... 9-2
DDR Software Primitives and Related Attributes ...................................................................................... 9-3
Memory Read Implementation .................................................................................................................. 9-9
Memory Write Implementation ................................................................................................................ 9-13
Design Rules/Guidelines......................................................................................................................... 9-16
DDR Input Module................................................................................................................................... 9-18
DDR Output Module................................................................................................................................ 9-19
DDR Input Module................................................................................................................................... 9-21
DDR Output Module................................................................................................................................ 9-24
PLL Divider and Delay Blocks................................................................................................................. 10-1
PLL Inputs and Outputs .......................................................................................................................... 10-2
PLL Attributes.......................................................................................................................................... 10-3
PLL Attributes Definitions........................................................................................................................ 10-5
Dynamic Delay Adjustment (for EHXPLLB only)..................................................................................... 10-6
f
f
Example .................................................................................................................................................. 10-8
Including sysCLOCK PLLs in a Design................................................................................................... 10-8
Module Manager Usage.......................................................................................................................... 10-8
Direct Instantiation Into Source Code ................................................................................................... 10-10
VCO
PFD
Constraint ........................................................................................................................................ 10-7
Constraint ....................................................................................................................................... 10-7
4
LatticeECP/EC Family Data Sheet
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