LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 9

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

June 2004
Features
Table 1-1. LatticeECP/EC Family Selection Guide
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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PFU/PFF Rows
PFU/PFF Columns
PFUs/PFFs
LUTs (K)
Distributed RAM (Kbits)
EBR SRAM (Kbits)
EBR SRAM Blocks
sysDSP Blocks
18x18 Multipliers
V
Number of PLLs
Packages and I/O Combinations:
100-pin TQFP (14 x 14 mm)
144-pin TQFP (20 x 20 mm)
208-pin PQFP (28 x 28 mm)
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
1. LatticeECP devices only.
CC
Extensive Density and Package Options
sysDSP™ Block (LatticeECP™ Versions)
Embedded and Distributed Memory
Flexible I/O Buffer
Voltage (V)
• 1.5K to 41K LUT4s
• 65 to 576 I/Os
• Density migration supported
• High performance multiply and accumulate
• 4 to 10 blocks
• 18 Kbits to 645 Kbits sysMEM™ Embedded
• Up to 163 Kbits distributed RAM
• Flexible memory resources:
• Programmable sysIO™ buffer supports wide
Block RAM (EBR)
range of interfaces:
− 4 to 10 36x36 multipliers or
– 16 to 40 18x18 multipliers or
− 32 to 80 9x9 multipliers
− Distributed and block memory
Device
1
1
LFEC1
192
112
1.5
1.2
12
16
18
67
97
—
—
6
2
2
LatticeECP/EC Family Data Sheet
LFEC3
384
145
160
3.1
1.2
16
24
12
55
67
97
—
—
6
2
1-1
LFECP6
LFEC6/
768
147
195
224
6.1
1.2
24
32
25
92
10
16
97
4
2
Dedicated DDR Memory Support
sysCLOCK™ PLLs
System Level Support
Low Cost FPGA
• Implements interface up to DDR333 (166MHz)
• Up to 4 analog PLLs per device
• Clock multiply, divide and phase shifting
• IEEE Standard 1149.1 Boundary Scan, plus
• SPI boot flash interface
• 1.2V power supply
• Features optimized for mainstream applications
• Low cost TQFP and PQFP packaging
ispTRACY™ internal logic analyzer capability
− LVCMOS 3.3/2.5/1.8/1.5/1.2
− LVTTL
− SSTL 3/2 Class I, II, SSTL18 Class I
− HSTL 18 Class I, II, III, HSTL15 Class I, III
− PCI
− LVDS, Bus-LVDS, LVPECL
LFECP10
LFEC10/
1280
10.2
277
147
195
288
1.2
32
40
41
30
20
5
4
LFECP15
LFEC15/
1920
15.4
350
195
352
1.2
40
48
61
38
24
6
4
Introduction
LFECP20
LFEC20/
2464
19.7
Advance Data Sheet
424
360
400
1.2
56
79
44
46
28
7
4
Introduction_01
LFECP40
LFEC40/
5120
41.0
164
645
496
576
1.2
64
80
70
10
40
4