LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 117

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 8-9. Pseudo Dual Port Memory Module Generated by Module Manager
The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block,
the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple EBR
block can be cascaded, in depth or width (as required to create these sizes).
The basic Pseudo Dual Port memory primitive for the LatticeECP/EC devices is shown in Figure 8-10.
Figure 8-10. Pseudo Dual Port RAM primitive or RAM_DP for LatticeECP/EC Devices
In the Pseudo Dual Port RAM mode, the input data and address for the ports are registered at the input of the
memory array. The output data of the memory is optionally registered at the output.
The various ports and their definitions for the Single Port Memory are included in Table 8-7. The table lists the cor-
responding ports for the module generated by the Module Manager and for the EBR RAM_DP primitive.
ADW[x:0]
WrAddress
WrClockEn
CS[2:0]
DI[y:0]
CLKW
WrClock
CEW
RST
WE
Reset
Data
WE
EBR based Pseudo
Dual Port Memory
RAM_DP
EBR
8-10
RdClock
RdClockEn
RdAddress
Q
ADR[x:0]
CLKR
CER
DO[y:0]
for LatticeECP/EC Devices
Memory Usage Guide for