LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 144

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 9-13. DDR Write Data Transfer for DQ Data
DQ PAD
FOR
FOR:
FOR:
CLK +180
CLK +270
ADDR/CMD
DQS PAD
DM PAD
DQ PAD
ONEG1
ONEG0
OPOS1
OPOS0
DQS
CLK
DM
DQ
(3)
(4)
(5)
(6)
(7)
(8)
(1)
(1)
(2)
(2)
Notes -
(1) OPOS1 and ONEG1 are the tristate inputs to the tristate block(ODDRXB)
(2) OPOS0 and ONEG0 are the 2 sets of data that are aligned with the CLK.
(3) CLK is the core clock that is used to generate all the DDR outputs in the user logic.
(4) CLK +180 is the inverted CLK. This clock is inverted to transmit the OPOS0 and OPOS1 data.
(5) CLK +270 is the phase of the CLK used to generate the DQS strobe output and the Address /
(6) DQS is the strobe output that is sent to the memory device. Figure 9 show DQS generation.
(7) The DM signal is the Data Mask signal and should be in phase with the DQ data output.
(8) DQ is DDR data, this data needs to be center aligned with the DQS strobe signal when it reaches the
Command output signals.
memory.
Preamble
P0
N0
P0
Write First Edge
N0
Mask
P1
N1
9-15
P1
Write Last Edge
N1
P2
N2
Lattice ECP/EC DDR Usage Guide
P2
N2
Postamble
TP0
TP0