LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 143

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LFEC10E-3F256C

Manufacturer Part Number
LFEC10E-3F256C
Description
Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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Lattice Semiconductor
Figure 9-12. Software Primitive Implementation for Memory Write
Write Timing Waveforms
Figures 9-13 and 9-14 show DDR write side data transfer timing for the DQ Data pad and the DQS Strobe Pad.
When writing to the DDR memory device, the DM (Data Mask) and the ADDR/ CMD (Address and Command) sig-
nals are also sent to the memory device along with the data and strobe signals.
CLK
User logic)
(From
PLL
CLK
CLK + 90
D
D
D
D
D
Q
Q
Q
Q
Q
User logic)
(From
Core Logic
OPOS1
ONEG1
OPOS0 = “0”
ONEG0 = “1”
OPOS1
ONEG1
OPOS0
ONEG0
“1”
“0”
“0”
“1”
PIO Logic
9-14
D
CLK
DA
DB
LSR
CLK
DA
DB
LSR
CLK
DA
DB
LSR
CLK
DA
DB
LSR
CLK
DA
DB
LSR
CLK
DA
DB
LSR
CLK
DA
DB
LSR
ODDRXB
ODDRXB
ODDRXB
ODDRXB
ODDRXB
ODDRXB
ODDRXB
Lattice ECP/EC DDR Usage Guide
Q
Q
Q
Q
Q
Q
Q
Q
ADDR/
CLKP
CLKN
CMD
DQS
DQ
DM
DDR Memory
Device

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