LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 218

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
TDO
The Test Data Output pin is used to shift out serial test instructions and data. When TDO is not being driven by the
internal circuitry, the pin will be in a high impedance state.
TDI
The Test Data Input pin is used to shift in serial test instruction and data. An internal pull-up resistor on the TDI pin
is provided. The internal resistor is pulled up to V
TMS
The Test Mode Select pin controls test operations on the TAP controller. On the falling edge of TCK, depending on
if TMS is high or low, a transition will be made in the TAP controller state machine. An internal pull-up resistor on
the TMS pin is provided. The internal resistor is pulled up to V
TCK
The test clock pin TCK provides the clock to run the TAP controller, loading and reloading the data and instruction
registers. TCK can be stopped in either the high or low state and can be clocked at frequencies up to the frequency
indicated in the device data sheet. The TCK pin supports hysteresis, with the value shown in the DC parameter
table of the data sheet.
Optional TRST
The JTAG Test Reset pin TRST in not supported in the LatticeECP/EC devices.
V
JTAG V
voltage.
Configuration and JTAG Pin Physical Description
All of the control pins and programming bus default to LVCMOS. The bank V
the sysCONFIG pins. The JTAG pin voltage levels are determined by the V
JTAG pin by V
In-System Programming Design Guidelines for ispJTAG Devices, available on the Lattice web site at www.lattices-
emi.com.
CCJ
CC
supplies independent power to the JTAG port to allow chaining with other JTAG devices at a common
CCJ
allows the device to support different JTAG chain voltages. For further JTAG chain questions, see
CCJ.
13-4
Lattice ECP/EC sysCONFIG Usage Guide
CCJ.
CCO
CCJ
pin determines the voltage level of
pin voltage level. Controlling the