LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 216

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Lattice ECP/EC sysCONFIG Usage Guide
Dedicated Control Pins
The following is a description of the LatticeECP/EC’s dedicated sysCONFIG pins used for controlling configuration.
CFG[0:2]
The Configuration Mode pins CFG[0:2] are input pins. They are used to select the configuration mode. Depending
on the configuration mode selected, different groups of dual-purpose configuration pins will be activated on Power-
On-Reset or when the PROGRAMN pin is driven low.
PROGRAMN
The PROGRAMN pin is an input to the device used to initiate a Programming sequence. A high to low signal
applied to the pin sets the device into configuration mode. The PROGRAMN pin can be used to trigger program-
ming other than at powering up. If the device is using JTAG, the device will ignore the PROGRAMN pin until the
device is released from the JTAG mode.
INITN
The INITN pin is a bidirectional open drain control pin. It is capable of driving a low pulse out as well as detecting a
low pulse driven in. When the PROGRAMN Pin is driven low or after the Power-On-Reset reset signal is released
during Power-up, the INITN pin will be driven low to reset the configuration circuitry and the External PROM. The
configuration memory will be cleared and the INITN pin will remain low as long as the PROGRAMN pin is low. To
delay configuration the INITN pin can be held low externally. The device will not enter configuration mode as long
as the INITN pin is held low.
During configuration, the INITN pin becomes an error detection pin. It will be driven low whenever a configuration
error occurs.
DONE
The DONE pin is a bidirectional control pin. It can be configured as an open drain or active drive control pin. The
DONE pin will be driven low when the device is in configuration mode and the internal DONE bit is not pro-
grammed. When the INITN and PROGRAMN pins are high and the DONE bit is programmed, the DONE pin will be
released. An open drain DONE pin can be held low externally and, depending on the wake-up sequence selected,
the device will not become functional until the DONE pin is released.
CCLK
The CCLK pin is a bi-directional pin. The direction depends on whether a Master Mode or Slave Mode is selected.
If a Master Mode is selected when the CFG pins are sampled, the CCLK pin will become an output pin; otherwise
CCLK will become an input pin. If the CCLK pin becomes an output pin, the internal programmable oscillator is
connected to the CCLK and is driven out to slave devices. CCLK will stop 100 to 500 clocks cycles after the DONE
pin is brought high and the device wake-up sequence completed. The extra clock cycles are provided to ensure
that enough clock cycles are provided to wake up other devices in the chain. When stopped, CCLK will become tri-
stated as an input. The CCLK will restart on the next configuration initialization sequence such as the PROGRAMN
pin being toggled. The MCCLK_FREQ Parameter controls the CCLK Master frequency. See the Master Clock
Selection section of this document for more information.
Dual-Purpose sysCONFIG Pins
The following is a list of dual-purpose sysCONFIG pins. If any of these pins are used for configuration they will not
be available as I/O after configuration. After configuration these pins are tristated and weakly pulled up.
DI/CSSPIN
The DI/CSSPIN dual-purpose pin is designated as DI (Data Input) for all of the serial bit stream configurations such
as Slave Serial. DI supports an internal weak pull up. When a serial mode is selected, the DI pin can become an
I/O when not used in a configuration mode.
In either SPI3 or SPIX mode, the DI/CSSPIN becomes the dedicated Chip Select output to drive the SPI Flash chip
select. CSSPIN will drive high when the LatticeECP/EC device is not in the process of configuration through the
SPI Port.
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