LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 153

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
end
end structure;
DDR Output Module
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library ec;
use ec.components.all;
entity ddr_example is
end ddr_example;
architecture structure of ddr_example is
signal DQS_data_DA_Q, DQS_data_DB_Q :std_logic;
signal DQS_data_DA_Q1, DQS_data_DB_Q1 :std_logic;
signal OUTDDR_data_DA_Q, OUTDDR_data_DB_Q:std_logic_vector(7 downto 0);
signal vcc_net : std_logic;
signal gnd_net : std_logic;
signal clkn : std_logic;
--DDR Output
component ODDRXB
end component;
component xpll_s
signal clk : std_logic;
signal clkp : std_logic;
signal pllclk : std_logic;
signal zero_dly : std_logic;
signal lead_lag : std_logic;
signal clkok : std_logic;
signal plldly : std_logic_vector(3 downto 0);
port(
port(
process reg0;
DQS_data_DB: in std_logic;
CLK
DA
DB
LSR
Q
port(DQ
RST
CLKI
CLKFB
DDAMODE
DDAIZR
DDAILAG
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: out STD_LOGIC);
DQS : out std_logic;
REFCLK : in std_logic;
RESET : in std_logic;
CLKOUTN: out std_logic;
CLKOUTP: out std_logic;
OUTDDR_data_DA: in std_logic_vector(7 downto 0);
OUTDDR_data_DB: in std_logic_vector(7 downto 0);
DQS_data_DA: in std_logic;
CLKLOCK
: out std_logic_vector(7 downto 0);
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: out std_logic);
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Lattice ECP/EC DDR Usage Guide