LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 161

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LFEC10E-3F256C

Manufacturer Part Number
LFEC10E-3F256C
Description
Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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LatticeECP/EC sysCLOCK PLL
Lattice Semiconductor
Design and Usage Guide
LOCK Output
The LOCK output provides information about the status of the PLL. After the device is powered up and the input
clock is valid, the PLL will achieve lock within the specified lock time. Once lock is achieved, the PLL lock signal will
be asserted. If, during operation, the input clock or feedback signals to the PLL become invalid, the PLL will lose
lock. The LOCK signal is available to the FPGA routing.
PLL Attributes
The PLL utilizes several attributes that allow the configuration of the PLL through source constraints. The following
section details these attributes and their usage.
FIN
The input frequency can be any value within the specified frequency range based on the divider settings.
CLKI_DIV, CLKFB_DIV, CLKOP_DIV, CLKOK_DIV
These dividers determine the output frequencies of each output clock. The user is not allowed to input an invalid
combination; determined by the input frequency, the dividers, and the PLL specifications.
FDEL
The FDEL attribute is used to pass the Delay Adjustment step associated with the Output Clock of the PLL. This
allows the user to advance or retard the Output Clock by the step value passed multiplied by 250ps(nominal). The
step ranges from -8 to +8 resulting the total delay range to +/- 2ns.
PHASEADJ
The PHASEADJ attribute is used to select Coarse Phase Shift for CLKOS output. The phase adjustment is pro-
grammable in 45° increments.
DUTY
The DUTY attribute is used to select the Duty Cycle for CLKOS output. The Duty Cycle is programmable at 1/8 of
the period increment.
WAKE_ON_LOCK
The WAKE_ON_LOCK cell determines if the device will wait for the PLL to lock before beginning the wake-up pro-
cess. If the attribute is set to “ON”, the device will not wake up until the LOCK signal for the given PLL is active.
DELAY_CNTL
This attribute is designed to select the Delay Adjustment mode. If the attribute is set to “DYNAMIC” the delay con-
trol switches between Dynamic and Static depending upon the input logic of DDAMODE pin. If the attribute is set to
“STATIC”, Dynamic Delay inputs are ignored in this mode.
LatticeECP/EC PLL Primitive Definitions
Two PLL primitives may be used for LatticeECP/EC PLL implementation. Users can choose either primitive
depending on the design requirement of the PLL. The definitions of the PLL I/O ports are shown in Table 10-2.
Some of the features are optional as shown in the table below.
Figure 10-2 shows the LatticeECP/EC PLL primitives library symbols and Table 10-1 lists the signals.
The EPLLB is a scaled down version of the PLL and is for users who do not need to use all the high performance
features. Users may choose not to use optional features available in this primitive.
The EHXPLLB includes all features available in the PLL including Dynamic Delay Adjustment. Some of the features
are optional as shown in Table 10-1.
10-3

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