LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 110

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Memory Usage Guide for
Lattice Semiconductor
for LatticeECP/EC Devices
Users can change the directory where the generated module files will be placed by clicking the browse button in
the Project Path.
The Module Name text box allows users to specify the entity name for the module they are about to generate.
Users must provide this entity name.
Design Entry, Verilog or VHDL, by default is the same as the project type. If the project is a VHDL project, the
selected Design Entry option will be “Schematic/ VHDL”, and “Schematic/ Verilog-HDL” if the project type is Verilog-
HDL.
The Device pull-down menu allows users to select different devices within the same family (LatticeEC in this exam-
ple). Then click the Customize button. This opens another window (Figure 8-3) where the RAM can be custom-
ized.
Figure 8-3. Example Generating Pseudo Dual Port RAM (RAM_DP) Module Customization – General
Options
The the left-hand side of this window shows the block diagram of the module. The right-hand side has two tabs –
the General Options tab and the Configuration tab.
In the General Options tab, users are given the option to generate an EDIF netlist along with Verilog-HDL or VHDL
Module. The Bus Expression Style and the Bus Ordering Style can also be selected.
Checking Insert I/O Buffers into the Netlist, inserts buffers into the netlist that is generated.
The Configuration tab allows users to specify the address port sizes and data widths. Selecting the Configuration
tab opens a window as shown in Figure 8-4.
8-3