LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 147

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Appendix A. Verilog Example of DDR Input and Output Modules
DDR Input Module
module ddr_in (DQ, DQS, CLK, RESET, UDDCNTL, READ, INDDR_DA, INDDR_DB, DQSCIB, PRMBDET, DLL_LOCK,
DDRCLKPOL);
input [7:0] DQ;
input DQS;
input CLK, RESET, UDDCNTL, READ;
output [7:0]INDDR_DA;
output[7:0] INDDR_DB;
output DQSCIB, PRMBDET, DLL_LOCK, DDRCLKPOL;
wire vcc_net,gnd_net;
wire dqsbuf, dqsdel, CLK, ddrclkpol_sig;
wire [7:0] INDDR_DA_sig;
wire [7:0] INDDR_DB_sig;
reg [7:0]INDDR_DA;
reg [7:0] INDDR_DB;
assign vcc_net = 1'b1;
assign gnd_net = 1'b0;
assign DDRCLKPOL = ddrclkpol_sig;
IDDRXB UL0 (.D(DQ[0]), .ECLK(dqsbuf), .SCLK(CLK), .CE(vcc_net), .DDRCLKPOL(ddrclkpol_sig),
IDDRXB UL1 (.D(DQ[1]), .ECLK(dqsbuf), .SCLK(CLK), .CE(vcc_net), .DDRCLKPOL(ddrclkpol_sig),
IDDRXB UL2 (.D(DQ[2]), .ECLK(dqsbuf), .SCLK(CLK), .CE(vcc_net), .DDRCLKPOL(ddrclkpol_sig),
IDDRXB UL3 (.D(DQ[3]), .ECLK(dqsbuf), .SCLK(CLK), .CE(vcc_net), .DDRCLKPOL(ddrclkpol_sig),
IDDRXB UL4 (.D(DQ[4]), .ECLK(dqsbuf), .SCLK(CLK), .CE(vcc_net), .DDRCLKPOL(ddrclkpol_sig),
IDDRXB UL5 (.D(DQ[5]), .ECLK(dqsbuf), .SCLK(CLK), .CE(vcc_net), .DDRCLKPOL(ddrclkpol_sig),
IDDRXB UL6 (.D(DQ[6]), .ECLK(dqsbuf), .SCLK(CLK), .CE(vcc_net), .DDRCLKPOL(ddrclkpol_sig),
IDDRXB UL7 (.D(DQ[7]), .ECLK(dqsbuf), .SCLK(CLK), .CE(vcc_net), .DDRCLKPOL(ddrclkpol_sig),
always@(posedge CLK)
begin
end
INDDR_DA = INDDR_DA_sig;
INDDR_DB = INDDR_DB_sig;
.LSR(RESET), .QA(INDDR_DA_sig[0]), .QB(INDDR_DB_sig[0]));
.LSR(RESET), .QA(INDDR_DA_sig[1]), .QB(INDDR_DB_sig[1]));
.LSR(RESET), .QA(INDDR_DA_sig[2]), .QB(INDDR_DB_sig[2]));
.LSR(RESET), .QA(INDDR_DA_sig[3]), .QB(INDDR_DB_sig[3]));
.LSR(RESET), .QA(INDDR_DA_sig[4]), .QB(INDDR_DB_sig[4]));
.LSR(RESET), .QA(INDDR_DA_sig[5]), .QB(INDDR_DB_sig[5]));
.LSR(RESET), .QA(INDDR_DA_sig[6]), .QB(INDDR_DB_sig[6]));
.LSR(RESET), .QA(INDDR_DA_sig[7]), .QB(INDDR_DB_sig[7]));
9-18
Lattice ECP/EC DDR Usage Guide