LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 137

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
VHDL Usage:
--Component declaration
component IDDRXB
end component;
--Module instantiation
UL0 : IDDRXB PORT MAP( D
Verilog Usage:
//Module instantiation
IDDRXB UL0 (.D(DQ[0]), .ECLK(dqsbuf), .SCLK(CLK), .CE(vcc_net),
ODDRXB
The ODDRXB primitive implements both the write and the tristate functions. This primitive is used to output DDR
data and the DQS strobe to the memory. The CKP and CKN can also be generated using this primitive. All the DDR
output tristate implementations are also implemented using the same primitive.
Figure 9-8 shows the ODDRXB primitive symbol and its I/O ports.
Figure 9-8. ODDRXB Symbol
Table 9-5 provides a description of all I/O ports associated with the ODDRXB primitive.
port(
D
ECLK
SCLK
CE
DDRCLKPOL: in STD_LOGIC;
LSR
QA
QB
.DDRCLKPOL(ddrclkpol_sig),.LSR(RESET),
.QA(INDDR_DA[0]),
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
: out STD_LOGIC;
: out STD_LOGIC);
ECLK
SCLK
CE
DDRCLKPOL=>ddrclkpol_sig,
LSR
QA
QB
=> dqsbuf,
=> CLK,
=> vcc_net,
=>RESET,
=>INDDR_DA(0),
=> INDDR_DB(0))
=> DQ(0),
.QB(INDDR_DB[0]));
CLK
DA
DB
LSR
ODDRXB
9-8
Q
Lattice ECP/EC DDR Usage Guide