LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 56

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LFEC10E-3F256C

Manufacturer Part Number
LFEC10E-3F256C
Description
Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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Lattice Semiconductor
LatticeECP/EC Internal Timing Parameters
1. Internal parameters are characterized but not tested on every device.
2. These parameters apply to LatticeECP devices only.
t
t
t
t
PLL Parameters
t
t
t
DSP Block Timing
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
HWREN_EBR
SUCE_EBR
HCE_EBR
RSTO_EBR
RSTREC
RSTSU
RSTW
SUI_DSP
HI_DSP
SUP_DSP
HP_DSP
SUO_DSP
HO_DSP
COI_DSP
COP_DSP
COO_DSP
COOVRFL_DSP
SUADSUB
HADSUB
SUSIGN
HSIGN
SUACCSLOAD
HACCSLOAD
Parameter
Hold Write/Read Enable to PFU Memory
Clock Enable Setup Time to EBR Output
Register
Clock Enable Hold Time to EBR Output
Register
Reset To Output Delay Time from EBR Out-
put Register
Reset Recovery to Rising Clock
Reset Signal Setup Time
Reset Signal Pulse Width
Input Register Setup Time
Input Register Hold Time
Pipeline Register Setup Time
Pipeline Register Hold Time
Output Register Setup Time
Output Register Hold Time
Input Register Clock to Output Time
Pipeline Register Clock to Output Time
Output Register Clock to Output Time
Overflow Register Clock to Output Time
AdSub Setup Time
AdSub Hold Time
Sign Setup Time
Sign Hold Time
Accumulator Load Setup Time
Accumulator Load Hold Time
2
Description
Over Recommended Operating Conditions
3-14
-0.17
Min.
0.23
0.18
1.8
1
1
-5
(Continued)
Max.
1.47
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
-0.20
Min.
0.28
0.21
1.8
1
-4
Max.
1.76
-0.24
Min.
0.33
0.25
1.8
1
-3
Max.
2.05
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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