LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 121

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LFEC10E-3F256C

Manufacturer Part Number
LFEC10E-3F256C
Description
Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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Lattice Semiconductor
Figure 8-13. FIFO Module Generated by Module Manager
Figure 8-14. FIFO_DC Module Generated by Module Manager
LatticeECP/EC devices do not have a built in FIFO. These devices have an emulated FIFO and FIFO_DC. These
are emulated by creating a wrapper around the existing RAMs (like RAM_DP). This wrapper also includes address
pointer generation and FIFO flag generation logic which will be implemented external to the EBR block. Therefore,
in addition to the regular EBR usage, there is extra logic for the address pointer generation and FIFO flag genera-
tion.
A clock is always required as only synchronous write is supported. The various ports and their definitions for the
FIFO and FIFO_DC are included in Table 11.
CLKW
CLK
RST
CLKR
WE
RE
RST
DI
WE
RE
DI
EBR based First-In First-Out
EBR based First-In First-Out
Memory
Memory
8-14
FIFO
FIFO
DO
FF
AF
EF
AE
DO
FF
AF
EF
AE
for LatticeECP/EC Devices
Memory Usage Guide for

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