LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 19

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 2-9. PLL Diagram
Figure 2-10 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.
Figure 2-10. PLL Primitive
Table 2-5. PLL Signal Descriptions
CLKI
CLKFB
RST
CLKOS
CLKOP
CLKOK
LOCK
DDAMODE
DDAIZR
DDAILAG
DDAIDEL[2:0]
DDAOZR
DDAOLAG
DDAODEL[2:0]
CLKFB
(from Post Scalar
Divider output,
clock net or
external pin
Signal
(from routing or
external pin)
CLKI
RST
CLKFB
CLKI
Input Clock
I/O
Divider
O
O
O
O
O
O
O
(CLKI)
I
I
I
I
I
I
I
EPLLB
Feedback
(CLKFB)
Clock input from external pin or routing
PLL feedback input from PLL output, clocknet, routing or external pin
“1” to reset input clock divider
PLL output clock to clock tree (phase shifted/duty cycle changed)
PLL output clock to clock tree (No phase shift)
PLL output to clock tree through secondary clock divider
“1” indicates PLL LOCK to CLKI
Dynamic Delay Enable. “1” Pin control (dynamic), “0”: Fuse Control (static)
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead
Dynamic Delay Input
Dynamic Delay Zero Output
Dynamic Delay Lag/Lead Output
Dynamic Delay Output
Divider
Dynamic Delay Adjustment
Adjust
Delay
CLKOP
LOCK
Controlled
Oscillator
DDAIDEL[2:0]
Voltage
VCO
DDA MODE
DDAILAG
2-9
DDAIZR
CLKFB
CLKI
RST
Post Scalar
(CLKOP)
Divider
Description
EHXPLLB
LatticeECP/EC Family Data Sheet
Phase/Duty
Secondary
(CLKOK)
Divider
Select
Clock
CLKOP
CLKOS
CLKOK
LOCK
DDAOZR
DDAOLAG
DDAODEL[2:0]
LOCK
CLKOS
CLKOP
CLKOK
Architecture