LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 115

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
The generated module makes use of the RAM_DP_TRUE primitive. For memory sizes smaller than one EBR
block, the module will be created in one EBR block. In cases where the specified memory is larger than one EBR
block, multiple EBR blocks can be cascaded, in depth or width (as required to create these sizes).
The basic memory primitive for the LatticeECP/EC devices, RAM_DP_TRUE, is shown in Figure 8-8.
Figure 8-8. True Dual Port RAM Primitive or RAM_DP_TRUE for LatticeECP/EC Devices
In True Dual Port RAM mode, the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
The various ports and their definitions for the True Dual Memory are included in Table 8-4. The table lists the corre-
sponding ports for the module generated by Module Manager and for the EBR RAM_DP_TRUE primitive.
Table 8-4. EBR-based True Dual Port Memory Port Definitions
Reset (or RST) only resets the input and output registers of the RAM. It does not reset the contents of the memory.
CS, or Chip Select, a port available in the EBR primitive, is useful when memory requires multiple EBR blocks to be
cascaded. The CS signal would form the MSB for the address when multiple EBR blocks are cascaded. CS is a 3-
bit bus, so it can easily cascade eight memories. However, if the memory size specified by the user requires more
than eight EBR blocks, the software automatically generates the additional address decoding logic, which is imple-
mented in the PFU external to the EBR blocks.
ClockA, ClockB
ClockEnA, ClockEnB
AddressA, AddressB
DataA, DataB
QA, QB
WEA, WEB
ResetA, ResetB
—
Generated Module
Port Name in
CLKA, CLKB
CEA, CEB
ADA[x:0], ADB[x:0]
DIA[y:0], DIB[y:0]
DOA[y:0], DOB[y:0]
WEA, WEB
RSTA, RSTB
CSA[2:0], CSB[2:0]
Port Name in the EBR
Block Primitive
ADA[x:0]
DOA[y:0]
CSA[2:0]
DIA[y:0]
RSTA
CLKA
WEA
CEA
Clock for PortA and PortB
Clock Enables for Port CLKA and CLKB
Address Bus Port A and Port B
Input Data Port A and Port B
Output Data Port A and Port B
Write Enable Port A and Port B
Reset for Port A and Port B
Chip Selects for Each Port
EBR
8-8
Description
CLKB
CEB
RSTB
WEB
CSB[2:0]
DOB[y:0]
ADB[x:0]
DIB[y:0]
for LatticeECP/EC Devices
Memory Usage Guide for
Rising Clock Edge
Active High
—
—
—
Active High
Active High
—
Active State