LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 226

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Boundary Scan and BSDL Files
The LatticeECP/EC BSDL files can be found on the Lattice Semiconductor web site. The boundary scan ring will
cover all the I/O pins, dedicated and dual-purpose sysCONFIG pins. The sysCONFIG pins can be observed using
the Boundary Scan.
Configuration Flow
The writing to the configuration SRAM memory can generally be split into three phases.
2. Load configuration data into the memory.
The Wake-up sequence puts the device into functional mode after full configuration. Choosing a proper Wake-up
sequence is important, to prevent contention.
The following sections describe the three steps to configure LatticeECP/EC devices.
Clearing the Configuration Memory
Two possible methods can clear the internal configuration memory of the LatticeECP/EC device. The first is when
the device powers up, the second is by toggling the PROGRAMN pin.
Power-up Sequence
On power-up the device tri-states all the I/Os, and sets the INITN and DONE pin to low. The device prepares for
configuration by resetting the configuration circuitry, clearing the DONE bit, and CRC registers. The device clears
the configuration memory and gets ready to start configuration. The JTAG port is ready to be used as soon as the
device clears the configuration memory.
After the device clears the POR, the device samples the Configuration Mode pins CFG[0:2] and recovers the rele-
vant configuration pins according to the Configuration Mode pin settings. The device will then release the INITN pin
if the PROGRAMN pin is high. If a Master Mode is selected, the device starts driving the master clock out of the
CCLK pin. The INITN pin can be driven low externally to delay device configuration. Once the INITN pin goes high,
the device is ready for configuration to start.
Toggling the PROGRAMN Pin
After a device is powered up, toggling the PROGRAMN pin will initiate a sequence to prepare the LatticeECP/EC
device for re-configuration from an external memory source. Upon driving the PROGAMN pin low, the INITN and
DONE pins will drive low and the memory will start clearing. The I/O pins will become tri-stated and pulled up to
V
Upon driving the PROGRAMN pin high, the CFG[0:2] are sampled to determine the configuration mode to imple-
ment as well as which configuration pins will be used for configuration. If a master mode is selected, the master
clock will start to be driven out CCLK. The INITN pin will be released once the configuration memory is cleared and
the PROGRAMN pin is driven high. Holding the INITN pin low will delay configuration. Configuration will begin as
soon as the INITN pin is released and pulled high.
Loading the Configuration Memory
Once the PROGRAMN and INITN pins are high, configuration can begin. Depending on the configuration mode
selected, data will be accepted on either the DI or D[0:7] pins on the rising edge of CCLK. If an error occurs at any
CCIO.
Loading the bit stream from DI or D[0:7], depending on the selected configuration mode. The INITN pin is set to
low on any error and BUSY can be used to delay configuration
1. Clear the configuration memory.
3. Wake up the device.
After power-up or toggling the PROGRAMN pin low, the configuration memory is cleared automatically.
The INITN pin is driven high by the EC/ECP device when the device has finished clearing the configuration
memory and Done bit. The INITN pin can also be driven externally by the user to delay the configuration
process.
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Lattice ECP/EC sysCONFIG Usage Guide