ISPLSI2064-100LT Lattice Semiconductor Corp., ISPLSI2064-100LT Datasheet
ISPLSI2064-100LT
Specifications of ISPLSI2064-100LT
Available stocks
Related parts for ISPLSI2064-100LT
ISPLSI2064-100LT Summary of contents
Page 1
... Interconnectivity — Lead-Free Package Options Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
Page 2
Functional Block Diagram Figure 1. ispLSI 2064/A Functional Block Diagram Megablock I I/O 2 I/O 3 I I/O 6 I/O 7 I I/O 10 I/O 11 I/O 12 ...
Page 3
Absolute Maximum Ratings Supply Voltage V cc ................................................... Input Voltage Applied .............................. -2 Off-State Output Voltage Applied ........... -2 Storage Temperature ..................................... -65 to 150°C Case Temp. with Power Applied .................... -55 to 125°C Max. Junction ...
Page 4
Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST ...
Page 5
External Timing Parameters 4 TEST 2 PARAMETER # COND. t pd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay pd2 Clock Frequency with Internal Feedback max f – 4 Clock ...
Page 6
Internal Timing Parameters Over Recommended Operating Conditions 2 PARAMETER DESCRIPTION # Inputs t Input Buffer Delay din Dedicated Input Delay 21 GRP t grp GRP Delay 22 GLB t 4ptbp 4 Product Term Bypass Comb. Path Delay ...
Page 7
Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 GOE 0 Derivations of su, h and co from the Product Term Clock Logic ...
Page 8
Power Consumption Power consumption in the ispLSI 2064 and 2064A de- vices depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power Consumption vs fmax 160 ...
Page 9
Pin Description NAME PLCC PIN NUMBERS I I/O 3 26, 27, 28, 30, 31, 32, I I I/O 11 34, 35, 36, I I/O 15 38, 39, 40, I/O 16 ...
Page 10
Pin Description NAME TQFP PIN NUMBERS I I/O 3 17, 18, 19, I I/O 7 21, 22, 23, I I/O 11 29, 30, 31, I I/O 15 33, 34, 35, I/O 16 ...
Page 11
Pin Configuration ispLSI 2064/A 84-Pin PLCC Pinout Diagram I I I/O 60 ...
Page 12
Pin Configuration ispLSI 2064/A 100-Pin TQFP Pinout Diagram ...
Page 13
Part Number Description ispLSI XXXXX Device Family 1 2064 2064A Device Number Speed f 125 = 125 MHz max f 100 = 100 MHz max MHz max 1. Discontinued per PCN #02-06. Contact Rochester Electronics for ...
Page 14
Ordering Information (Cont.) Lead-Free Packaging FAMILY fmax (MHz) tpd (ns) 125 125 100 ispLSI 100 84-PLCC lead-free package is MSL4. Refer to “Handling Moisture Sensitive Packages” document on www.latticesemi.com. FAMILY fmax (MHz) tpd (ns) 81 ...