LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 91

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 7-1. sysIO Banking
V
Each bank has a separate V
such as LVTTL, LVCMOS, and PCI. LVTTL, LVCMOS3.3, LVCMOS2.5 and LVCMOS1.2 also have fixed threshold
options allowing them to be placed in any bank. The VCCIO voltage applied to the bank determines the ratioed
input standards that can be supported in that bank. It is also used to power the differential output drivers.
V
In addition to the bank V
that powers the differential and referenced input buffers. V
headroom to satisfy the common-mode range requirements of these drivers and input buffers.
V
The JTAG pins have a separate V
mines the electrical characteristics of the LVCMOS JTAG pins, both the output high level and the input threshold.
Input Reference Voltage (V
Each bank can support up to two separate V
for the referenced input buffers. The location of these V
be used as regular I/Os if the bank does not require a V
V
When interfacing to DDR memory, the V
input from the memory. A voltage divider between V
CCIO
CCAUX
CCJ
REF1
(1.2V/1.5V/1.8V/2.5V/3.3V)
(1.2V/1.5V/1.8V/2.5V/3.3V)
for DDR Memory Interface
(3.3V)
CCIO
V
V
V
V
V
V
GND
GND
REF1(7)
REF2(7)
CCIO7
CCIO6
REF2(6)
REF1(6)
CCIO
supplies, devices have a V
supply that powers the single-ended output drivers and the ratioed input buffers
REF1,
CCJ
power supply that is independent of the bank V
V
REF1
REF2
REF
input must be used as the reference voltage for the DQS and DQ
Bank 0
Bank 5
)
input voltages, V
REF1
REF
REF
7-3
CC
and GND is used to generate an on-chip reference volt-
CCAUX
core logic power supply, and a V
pins is pre-determined within the bank. These pins can
voltage.
Bank 1
Bank 4
REF1
is required because V
LatticeECP/EC sysIO Usage Guide
and V
REF2
, that are used to set the threshold
V
V
V
V
V
V
GND
GND
REF1(2)
REF2(2)
REF2(3)
REF1(3)
CCIO2
CCIO3
CCIO
CC
does not have enough
CCAUX
supplies. V
auxiliary supply
CCJ
deter-