LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 219

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Configuration Modes
The LatticeECP/EC devices support many different types of configuration modes utilizing either serial or parallel
data inputs. On power-up or upon driving the PROGRAMN pin low, the CFG[2:0] pins are sampled to determine
the mode the devices will be configured in. Table 13-2 lists the Mode, CFG[0:2] state and the software
CONFIG_MODE parameters. The following subsections break down each configuration mode individually.
Table 13-2. Configuration Modes for the LatticeECP/EC Devices
Configuration Options
Several configuration options are available for each configuration mode. When daisy chaining multiple FPGA
devices, an overflow option is provided for serial and parallel configuration modes. When using a master clock, the
master clock frequency can be set within a range as determined by the device. By setting the proper parameter in
the Lattice design software, the selected configuration options are set in the generated bit stream. As the bit stream
is loaded into the device, the selected configuration options will take effect. These options are described in the fol-
lowing sections and are software selectable by the Lattice design software.
Bypass Option
The Bypass option is used in parallel and serial device daisy chains for a slave serial device. When the bypass
device has completed configuration and the Bypass option preference is selected, data coming into the device con-
figuration port will overflow serially out of DOUT to the DI of the next slave serial device. The Bypass configuration
selection is supported in the CONFIG_MODE selections as shown in Table 13-2.
In serial configuration mode, the Bypass option connects the DI to DOUT, via a bypass register upon completion of
configuration. The bypass register is initialized with a ‘1’ at the beginning of configuration. In parallel configuration
mode, the Bypass option causes the data incoming from D[0:7] to be serially shifted to DOUT after completion of
configuration. The serialized byte wide register will be shifted to DOUT through the bypass register. D7 of the byte
wide data will be shifted out first and followed by D6, D5, and so on.
Once the Bypass option starts, the device will remain in Bypass until the Wake-up sequence completes. One
option to get out of the Bypass option is to toggle CSN and CS1N, which will act as a reset signal. Refer to the
Master Parallel Mode section of this document for more details.
Flow Though Option
The Flow Through option pulls the CSON pin low when the device has completed its configuration. The Flow
Through option can be implemented with either Master or Slave Parallel configuration modes as referenced in
Table 13-2. The Flow Through option will drive out a static low signal on the CSON pin. The Flow Through option
will also tri-state the device D[0:7], INITN and BUSY pins when configuration is completed on the device in order to
not interfere with the next daisy chained device to be configured.
SPI3
SPIX
Master Serial (Bypass OFF)
Master Serial (Bypass ON)
Slave Serial (Bypass OFF)
Slave Serial (Bypass On)
Master Parallel (Flow Through OFF)
Master Parallel (Flow Through ON)
Slave Parallel
Slave Parallel (Bypass ON)
Slave Parallel (Flow Through ON)
ispJTAG (1149.1 interface)
Mode
CFG[2]
X
0
0
1
1
1
1
1
1
1
1
1
CFG[1]
13-5
X
0
0
0
0
0
0
1
1
1
1
1
Lattice ECP/EC sysCONFIG Usage Guide
CFG[0]
0
1
0
0
1
1
0
0
1
1
1
X
SPI3
SPIX
MASTER_SERIAL
MASTER_SERIAL_BYPASS
SLAVE_SERIAL (Default)
SLAVE_SERIAL_BYPASS
MASTER_PARLLEL
MASTER_PARLLEL_FLOWTHR
SLAVE_PARALLEL
SLAVE_PARALLEL_BYPASS
SLAVE_PARALLEL_FLOWTHR
Any CONFIG_MODE or NONE1
CONFIG_MODE Parameter