PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 53

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Direct Data Transfer Mode
A fourth register, the Bus Region Descriptor registers
(LASxBRD and/or EROMBRD), defines the Local Bus
characteristics for the PCI Target regions. (Refer to
Figure 4-5.)
Each PCI-to-Local Address space is defined as part of
reset initialization. (Refer to Section 4.2.1.8.1.) These
Local Bus characteristics can be modified at any time
before actual data transactions.
4.2.1.8.1
Range—Specifies the PCI Address bits to use for
decoding a PCI access to Local Bus space. Each bit
corresponds to a PCI Address bit. Bit 31 corresponds
to address bit 31. Write 1 to all bits required to be
included in decode, and 0 to all others.
Remap PCI-to-Local Addresses into a Local
Address Space—Bits in this register remap (replace)
the PCI Address bits used in decode as the Local
Address bits.
Local Bus Region Descriptor—Specifies the Local
Bus characteristics.
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
PCI Target Local Bus
Initialization
4.2.1.8.2
After a PCI reset and serial EEPROM load, the
software determines the amount of required address
space by writing all ones (1) to a PCI Base Address
register and then reading back the value. The
PCI 9030 returns zeros (0) in the Don’t Care Address
bits, effectively specifying the address space required,
at which time the PCI software maps the Local
Address space into the PCI Address space by
programming the PCI Base Address register. (Refer
to Figure 4-5.)
PCI Target Initialization
PCI Target (Direct Slave) Operation
Section 4
4-5