PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 44

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 3
Serial EEPROM Reset and Initialization
3.4
The PCI 9030 provides several internal registers,
which allow for maximum flexibility in the bus-interface
design
accessible from the PCI and Local Buses (refer to
Figure 3-2) and include the following:
• PCI Configuration
• Local Configuration
• Power Management
• Hot Swap
• VPD
Figure 3-2. PCI 9030 Internal Register Access
Note:
Memory- or I/O-Mapped. Access can be disabled by way of the
PCIBAR1 and PCIBAR0 Enable bits (CNTRL[13:12]). These bits
should not be disabled for the PC platform.
3.4.1
Device and Vendor IDs. There are two sets of Device
and Vendor IDs. The Device ID and Vendor ID are
located at offset 00h of the PCI Configuration registers
(PCIIDR[31:16]
The Subsystem ID and Subsystem Vendor ID are
located at offsets 2Eh and 2Ch, respectively, of the
PCI
PCISVID [15:0], respectively). The Device ID and
Vendor ID identify the particular device and its
manufacturer.
Subsystem ID provide a way to distinguish between
PCI interface chip vendors and add-in board
manufacturers, using a PCI chip.
3-6
Master
PCI
Bus
Configuration
Local Configuration register access can be limited to
INTERNAL REGISTER ACCESS
and
PCI Configuration Registers
performance.
The
and
Power Management
Hot Swap Registers
Local Configuration
PCI Configuration
registers
Subsystem
VPD Registers
PCI 9030
Registers
Registers
Registers
PCIIDR[15:0],
These
(PCISID[15:0]
Vendor
registers
respectively).
Master
Local
Bus
ID
and
and
are
Status. This register contains PCI Bus-related events
information.
Command. This register controls the ability of a
device to respond to PCI accesses. It controls whether
the device responds to I/O or Memory Space
accesses.
Class Code. This register identifies the general
function of the device. (Refer to PCI r2.2 for further
details.)
Revision ID. The value read from this register
represents the PCI 9030 current silicon revision.
Header Type. This register defines the device
configuration header format and whether the device is
single function or multi-function.
Note: Multiple functions are not supported.
Cache Line Size. This register defines the system
cache line size in units of 32-bit Lwords.
PCI Base Address for Memory Accesses to Local
Configuration Registers. The system BIOS uses this
register to assign a PCI Address space segment for
Memory accesses to the PCI 9030 Local Configuration
registers. The PCI Address Range occupied by these
Configuration registers is fixed at 128 bytes. During
initialization, the Host writes FFFFFFFF to this
register, then reads back FFFFFF80, determining the
required Memory space of 128 bytes. The Host then
writes the base address to PCIBAR0[31:7].
PCI Base Address for I/O Accesses to Local
Configuration Registers. The system BIOS uses
this register to assign a PCI address space segment
for I/O accesses to the PCI 9030 Local Configuration
registers. The PCI address range occupied by these
Configuration registers is fixed at 128 bytes. During
initialization, the host writes FFFFFFFF to this register,
then reads back FFFFFF81, determining a required
128 bytes of I/O space. The Host then writes the base
address to PCIBAR1[31:7].
© 2002 PLX Technology, Inc. All rights reserved.
PCI 9030 Data Book Version 1.4
Internal Register Access