PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 149

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Control Registers
Register 10-59. (CNTRL; 50h) PCI Target Response, Serial EEPROM, and Initialization Control (Continued)
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
22:19
Bit
16
17
18
23
24
25
26
27
28
29
30
31
PCI Read No Flush Mode. Value of 1 does not flush the Read FIFO if the
PCI Read cycle completes (PCI Target Read Ahead mode). Value of 0
flushes the Read FIFO if a PCI Read cycle completes. Read Ahead mode
requires that Prefetch be enabled in the LASxBRD and/or EROMBRD
registers for the Memory-Mapped spaces that use Read Ahead mode.
The PCI 9030 flushes its Read FIFO for each I/O-Mapped access.
PCI Read No Write Mode (PCI Retries for Writes). When the PCI r2.2
Features Enable bit is set (bit [14]=1), value of 1 forces a PCI Retry on writes
if a Delayed Read is pending. Value of 0 (or bit [14] =0) allows writes to occur
while a Delayed Read is pending.
PCI Write Release Bus Mode Enable. Value of 1 disconnects if the Write
FIFO becomes full. Value of 0 de-asserts TRDY# until space is available
in the Write FIFO (PCI Write Hold Bus mode).
PCI Target Retry Delay Clocks. Number of PCI clocks (multiplied by 8) from
the beginning of a PCI Target access, after which a PCI Retry is issued if the
transfer has not completed. Valid for Read cycles only if bit [14]=0. Valid for
Write cycles only if bit [18]=0.
PCI Target LOCK# Enable. Value of 1 enables PCI Target locked sequences.
Value of 0 disables PCI Target locked sequences.
Serial EEPROM Clock for PCI Bus Reads or Writes to Serial EEPROM.
Toggling this bit generates a serial EEPROM clock. (Refer to manufacturer’s
data sheet for the particular serial EEPROM being used.)
Serial EEPROM Chip Select. For PCI Bus reads or writes to the serial
EEPROM, setting this bit to 1 provides serial EEPROM chip select.
Write Bit to Serial EEPROM. For writes, this output bit is the input to serial
EEPROM. Clocked into the serial EEPROM by serial EEPROM clock.
Read Serial EEPROM Data Bit. For reads, this input bit is the output of serial
EEPROM. Clocked out of the serial EEPROM by serial EEPROM clock.
Serial EEPROM Present. Value of 1 indicates a blank or programmed serial
EEPROM is present.
Reload Configuration Registers. When set to 0, writing 1 causes the
PCI 9030 to reload the Local Configuration registers from serial EEPROM.
PCI Adapter Software Reset. Value of 1 resets the PCI 9030 and issues a
reset to the Local Bus (LRESETo# asserted). The PCI 9030 remains in this
reset condition until the PCI Host clears this bit. The contents of the PCI and
Local Configuration registers are not reset. The PCI Interface is not reset.
Note: If PCI Target Read Ahead mode is enabled (bit [16]=1), disable it prior
to a software reset, or if following a software reset, perform a PCI Target read
of any valid Local Bus address, except the next sequential Lword referenced
from the last PCI Target read, to flush the PCI Target Read FIFO.
Disconnect with Flush Read FIFO. When the PCI r2.2 Features Enable
bit is set (bit [14]=1), value of 1 causes acceptance of a new Read request
with flushing of the Read FIFO when a PCI Target Read request does not
match an existing, pending Delayed Read in the Read FIFO. Value of 0, or
clearing of the PCI r2.2 Features Enable bit (bit [14]=0), causes a new Target
Read request (different command, address and/or byte enables) to be Retried
when a Delayed Read is pending in the Read FIFO.
Description
Read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Write
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Value after
Section 10
Reset
Registers
Fh
—
0
0
0
0
0
0
0
0
0
0
0
10-35