PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 190

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

i960J function, not supported
to
i960J function, not supported
ID
idle bus state 2-3
IDSEL 11-7, 13-3, 13-6
IEEE Standard 1149.1-1990 11-18
IEEE Standard Test Access Port and Boundary-Scan
initialization 4-5
input, general purpose
INTA# 6-1, 10-11, 11-7, 13-3, 13-6
INTCSR 3-4, 6-2, 10-33
interface chip, target 1-3
Index-4
Data I/O for programming serial EEPROM values 3-2
general purpose 6-1–6-3, 11-3, 11-9, 13-3, 13-6
GPIOC register 10-36–10-37
Hot Swap requirement 8-1
initialization control (CNTRL) 10-34–10-35
insertion and extraction, during 8-2
mapped accesses 1-3
mapped configuration registers 10-2
pin type 11-3, 11-7, 11-11, 11-13, 11-16
read 2-1
SMARTarget 1-1
space access 10-4, 10-7, 10-8, 10-9, 10-16, 10-17,
tolerance 1-4
write 2-1
2-10
capability 10-2
class code 9-1
configuration 10-4
device 1-4, 1-5, 3-1, 9-1, 10-2, 10-4
Hot Swap 8-4, 10-14
network 1-4
new capability function 10-5
power management 7-1, 10-1, 10-12
revision 3-3, 3-6, 9-1, 10-2, 10-5
silicon revision 1-4, 10-5
subsystem and subsystem vendor 1-4, 3-1, 9-1, 10-2,
vendor 1-4, 1-5, 3-1, 9-1, 10-2, 10-4
VPD 9-1, 10-1, 10-15
See IEEE Standard 1149.1-1990
configuration timing diagrams 3-9–3-10, 4-14–4-15
control (CNTRL) register 10-3, 10-34–10-35
functional description 3-1
IDSEL 11-7
PCI 4-7
PMC 10-12
serial EEPROM 3-1–3-10
serial EEPROM (2K or 4K) timing diagram, from 3-8, 4-13
See general purpose I/O
LCLK
Architecture
10-19, 10-20
10-10
internal wait states 2-5, 2-7–2-8, 2-10, 4-1, 4-35,
interrupt
interrupts
IRDY# 2-1, 11-7, 13-3, 13-6
IRQ 6-1
ISA bus interface 1-5
J
JTAG 11-18
L
LA[23:2] 11-13, 11-16, 13-3, 13-6
LA[27:24] 11-3, 11-12, 11-15, 13-3, 13-6
LAD[31:0] 2-3, 11-3, 11-13, 13-3, 13-6
LAS0BA 3-3, 4-4, 4-7, 10-8, 10-19
LAS0BRD 2-8, 3-4, 4-3, 4-5, 10-21
LAS0RR 3-3, 4-4, 10-8, 10-16
LAS1BA 3-4, 4-4, 4-7, 10-8, 10-19
LAS1BRD 2-8, 3-4, 4-3, 4-5, 10-23
LAS1RR 3-3, 4-4, 10-8, 10-16
LAS2BA 3-4, 4-4, 10-9, 10-20
LAS2BRD 2-8, 3-4, 4-3, 4-5, 10-25
LAS2RR 3-3, 4-4, 10-9, 10-17
LAS3BA 3-4, 4-4, 10-9, 10-20
LAS3BRD 2-8, 3-4, 4-3, 4-5, 10-27
LAS3RR 3-3, 4-4, 10-9, 10-17
latency timer, PCI, not supported 10-2, 10-6
layers, routing, µBGA 13-7–13-8
LBE[3:0]# 2-4, 11-13, 11-16, 13-3, 13-6
LCLK
control/status 10-3, 10-33
controller 1-1, 1-3
disabled 7-1, 10-13
ENUM# 8-3, 10-14
generator 1-1, 1-3
input, LINT[2:1] 11-2, 11-10, 13-3, 13-6
line 10-2, 10-11
local
LSW 3-4
output set by ENUM# 11-7
PCI and Local 6-1–6-3
PCI Power Management functional description 7-1–7-3
pin 3-3, 10-2, 10-11
registers 3-7
request 6-1, 10-11, 11-7
timing diagrams 4-10, 6-4
wake-up event 11-8
ENUM# 8-4
11-1, 11-10, 12-2, 13-3, 13-6
10-21–10-29, 11-9, 11-14
level and edge-triggered 4-10, 6-4
LINTi1 and LINTi2 11-10
power management (LPMINT#) 7-3, 11-11
© 2002 PLX Technology, Inc. All rights reserved.
PCI 9030 Data Book Version 1.4