PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 32

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 2
PCI and Local Bus
2.2.3.4.3
2.2.4
The PCI 9030 is the Local Bus Master. The PCI 9030
interfaces a PCI Host Bus to a Multiplexed or
Non-Multiplexed
MODE[1:0] pins, as listed in Table 2-4.
Notes:
Internal registers are not readable/writable from the Local Bus.
The internal registers are accessible from the Host CPU on the
PCI Bus or from the serial EEPROM.
Table 2-4. MODE Pin-to-Bus Mode Cross-Reference
2.2.4.1
In both Non-Multiplexed and Multiplexed modes, the
LA[27:2] Address Bus drives an access address valid
beginning one clock prior to ADS# assertion (which
signals the start of the Bus cycle) and continues until
the cycle ends (signaled by BLAST# de-assertion).
In Multiplexed mode (MODE=1), the LAD/LD[31:0]
Multiplexed Address/Data Bus also drives the access
address valid onto LAD/LD[27:0], beginning one clock
prior to ADS# assertion and continuing until ADS# de-
assertion one clock later, after which data is driven.
The LAD/LD[31:0] Data Bus drives Write data valid
one
de-asserts, and continues until the cycle ends or until
data-to-address wait states (or data-to-data wait states
2-6
Timing Diagram 2-1. Local Bus Arbitration from the PCI 9030 by Another Local Bus Initiator (LREQ and LGNT)
Local Bus
MODE Pin
LREQ
LGNT
LCLK
clock
1
0
No PCI Initiator capability.
Local Bus Interface
and Bus Cycles
0ns
Bus Cycles
after
Arbitration Timing Diagram
Non-Multiplexed
Multiplexed
Local
Mode
ADS#
Local Bus is requested by another Local Initiator.
PCI 9030 grants the Local Bus to another Local Initiator; otherwise, remains low.
Bus,
Another Local Initiator Drives Bus
assertion
selected
32-, 16, or 8-Bit
Bus Width
when
by
250ns
1
ADS#
the
De-asserted if PCI 9030 needs to use a Local Bus and CNTRL[7]=0;
otherwise, remains high until the Local Initiator is done.
if burst is enabled) begin, if programmed. BLAST#
assertion indicates the last Data cycle of an access.
(Refer to Figure 2-2 and Figure 2-3.)
Write cycle data valid time and Read cycle data time
can be extended with internally generated address-to-
data wait states and/or by delaying READY# ready
input assertion if READY# input is enabled for the
Space. When enabled, READY# input assertion
indicates to the PCI 9030 that Read data on the bus is
valid to accept or a Write Data transfer has completed.
READY# input is not sampled until address-to-data
wait states (and/or data-to-data wait states with burst),
which are signaled by WAITo# assertion, expire
(WAITo# de-asserted). READY# is ignored during the
Address cycle (ADS# assertion), internally generated
data-to-address wait states, and idle cycles between
transfers. BTERM# input, if enabled, is used to break
up a Burst access and also serves as a ready input.
(Refer to Section 2.2.4.3.)
RD# and WR# strobes can be independently
programmed for each Local Address Space. RD# and/
or WR# strobe assertion can be optionally delayed
during address-to-data wait states. Write Cycle Hold
clocks can be selectively programmed to extend data
valid time and BLAST# assertion, beyond WR# strobe
de-assertion.
Recovery (idle) cycles can be optionally programmed
for each Space, using data-to-address wait states
(NXDA) to extend time between Local Bus accesses
to allow sufficient time for an external device to float its
data pins after a Read request.
© 2002 PLX Technology, Inc. All rights reserved.
500ns
PCI 9030 Data Book Version 1.4
Local Bus