PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 28

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 2
PCI and Local Bus
Byte merging is an optional function of a Host-to-PCI
or PCI-to-PCI bridge in which bytes or combinations of
bytes written in any order by multiple individual
Memory Write cycles to one Lword address can be
merged within the bridge’s Posted Memory Write
buffer into a single Lword Write cycle. Byte merging is
possible when any of the bytes to be merged are
written only once, and the Prefetchable bit(s) is set
to 1 (PCIBARx[3]=1).
The Prefetchable bit(s) setting has no effect on
prefetching initiated by the PCI 9030. PCI 9030
prefetching is disabled, by default, in the Local
Configuration registers, and should be enabled to
support highest performance with PCI Target Burst
reads and PCI Target Read Ahead mode. (Refer to
Section 4.2.1.4.)
2.1.1.5
Direct PCI access to an 8- or 16-bit Local Bus device
results in the PCI Bus Lword being broken into
multiple Local Bus transfers. For each 8-bit transfer,
byte enables are encoded to provide Local Address
bits LA[1:0]. For each 16-bit transfer, byte enables are
encoded to provide BLE#, BHE#, and LA1.
2-2
From PCI
From PCI
From PCI
To PCI
To PCI
PCI Target Accesses to an
8-or 16-Bit Local Bus Device
Config Data_Outbound
Config Data_Inbound
PCI Control
Address/Data
Data
Configuration
Figure 2-1. Local Bus Block Diagram
PCI Target
Registers
FIFOs
Feature Control
Local Control
Address/Data
2.2
2.2.1
The Local Bus provides a data path between the PCI
Bus and non-PCI devices, including memory devices
and peripherals. The Local Bus is a 32-bit multiplexed
or non-multiplexed bus, with bus memory regions that
can be programmed for 8-, 16-, or 32-bit widths. The
PCI 9030 Local Bus is signal-compatible with popular
RISC and Bridge architecture, including the i960Cx,
i960Jx, and PPC401 GF. In addition, the Local Bus
can directly connect to Texas Instruments DSP
devices
TMS320C54x).
The PCI 9030 is the Local Bus Master. The PCI 9030
can transfer data between the Local Bus, internal
registers and FIFOs. Burst lengths are not limited. The
bus width depends upon the Local Address Space
register setting. There are four address spaces and
one default space (the Expansion ROM that can be
used as another address space). Each space contains
a set of configuration registers that determine all Local
Bus characteristics when that space is accessed.
Data
Local Arbiter
Local Master
Controller
LOCAL BUS
Introduction
© 2002 PLX Technology, Inc. All rights reserved.
(such
Local/Data Control
as
Local Address/
Data Bus
PCI 9030 Data Book Version 1.4
the
TMS320C6202
LAD/LD[31:0]
LA[27:2]
Local Bus
and