PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 29

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Local Bus
2.2.1.1
Four types of transactions can occur on a Local Bus:
• Read
• Write
• Read Burst
• Write Burst
A Bus access is a transaction which is bounded by the
assertion of ADS# at the beginning and de-assertion
of BLAST# at the end. A Bus access consists of an
Address cycle followed by one or more Data transfers.
During each Clock cycle of an access, the Local Bus is
in one of four basic states defined in Section 2.2.1.2.
A Clock cycle consists of one Local Bus clock period.
2.2.1.2
The four basic bus states are idle, address, data/wait,
and recovery. Once the Local Bus Master owns the
bus and needs to start a bus access, the address state
is entered, ADS# or ALE is asserted, and a valid
address is presented on the address/data bus. Data is
then transferred while in a data/wait state. READY# or
the internal wait state generator is used to insert wait
states. BLAST# is asserted during the last data/wait
state to signify the last transfer of the access.
After all data is transferred, the bus enters the
recovery state to allow the bus devices to recover. The
bus then enters the idle state and waits for another
access.
2.2.2
The key Local Bus control signals listed in most timing
diagram examples are as follows:
• ADS# or ALE indicates the start of an access
• READY#, WAITo#, and BTERM# are used to
• LW/R# indicates the Data transfer direction
• BLAST# and BTERM# indicate the end of
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
insert wait states and terminate Burst cycles
during Data transfers
an access
Local Bus Signals Used in
Timing Diagrams
Transactions
Basic Bus States
The key data signals are:
• LA Address Bus
• LAD Address, Data Bus
• LBE[3:0]# Local Byte Enables, indicating valid
2.2.3
There are four groups of Local Bus signals:
• Clock
• Address/Data
• Control/Status
• Arbitration
Signal usage varies upon application.
2.2.3.1
LCLK, the Local Bus clock, operates at frequencies up
to 60 MHz, and is asynchronous to the PCI Bus clock.
Most Local Bus signals are driven and sampled on the
rising edge of LCLK. Setup and hold times, with
respect to LCLK, must be observed. (Refer to
Section 12.2, ”Local Inputs,” on page 12-3 for setup
and hold timing requirements.)
2.2.3.2
2.2.3.2.1
2.2.3.2.1.1
LA[27:2] contains the transfer address. The address
remains valid during the transfer, and increments with
successive data during Burst cycles.
2.2.3.2.1.2
The LAD[31:0] Bus is a 32-bit Multiplexed Address/
Data Bus. During an Address phase, LAD[27:0]
contains the transfer address, with LAD[1:0] having
the same state as LBE[1:0]# pins.
During Data phases, LAD[31:0], LAD[15:0], or
LAD[7:0] contain transfer data for a 32-, 16-, or 8-bit
bus, respectively. If the bus is 8 or 16 bits wide, the
data supplied by the PCI 9030 is replicated across the
entire 32-bit-wide bus.
byte lanes
Local Bus Signals
Clock
Address/Data
Multiplexed Mode (MODE=1)
LA[27:2]
LAD[31:0]
PCI and Local Bus
Section 2
2-3