PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 106

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 7
PCI Power Management
should change by monitoring the Power_State bits
(PMCSR[1:0]), by way of the LPMINT# interrupt
signal.
The PCI 9030 is a PCI Target device only; therefore,
there is no access to the internal registers from the
Local Bus. The Local Power Management Interrupt
output (LPMINT#) is included to accommodate the
PCI Power Management interface to a Local Bus.
The PCI 9030 asserts LPMINT# to request a Power
State change to an external Local Bus Initiator when
the
(PMCSR[1:0]) changes. The LPMINT# interrupt is
synchronous to the Local clock. When asserted, it is
one clock-wide pulse.
External Local glue logic is needed to latch the Power
State change and to retain the previous Power State
history for further evaluation by the external Local Bus
Initiator.
The
(PMC[15:11])
corresponding to a specific power state (PMCSR[1:0]).
PMC[15:11] are configured by way of the serial
EEPROM.
The Local Host then sets the PME_Status bit
(PMCSR[15]=1), by way of LPMESET, and the
PCI 9030 asserts PME#. To clear the PME_Status bit,
the PCI Host must write 1 to the status bit
(PMCSR[15]=1). To disable the PME# Interrupt signal,
either the PCI Host or serial EEPROM can write 0 to
the PME_En bit (PMCSR[8]=0).
The Local Power Management Enumerator Set
Interrupt
accommodate the PCI Power Management interface
to a Local Bus.
The external Local Bus Initiator can assert LPMESET
to the PCI 9030 Power Management Control/Status
register (PMCSR[15]) to set the PME# status and
assert the PME# signal in the case of a Wake-up
Request event to the PCI Bus.
LPMINT# output is asserted every time the power
state in the PMCSR register changes. Transition from
state 11 (D
and serial EEPROM reload. During a soft reset, the
Local Bus interface is in Reset mode. The PCI 9030
issues LRESETo# and resets the Local Bus and all its
Local Internal registers to their default values.
7-2
Power
PCI 9030
3hot
input
Management
) to state 00 (D
to
uses
(LPMESET)
identify
the
Control/Status
the
0
) causes a soft reset
PME_Support
is
PME#
included
Support
register
bits
to
In state D
disabled, as well as PCI interrupts, and only
configuration is allowed.
7.2.1
The Data_Scale bits (PMCSR[14:13]) indicate the
scaling factor to use when interpreting the value of the
Power Management Data bits (PMDATA[7:0]). The
value and meaning of the bits depend upon the data
value
(PMCSR[12:9]). The Data_Scale bit value is unique
for each Data_Select bit. For Data_Select values from
8 to 15, the Data_Scale bits always return a 0
(PMCSR[14:13]=0).
To accommodate the PCI Power Management
interface to a local bus, two hidden registers (loadable
by the serial EEPROM) are available to store all
necessary information for the Power Management
Data and Data_Scale register bits—(PMDATASEL;
PCI:70h) for PMDATA[7:0] and (PMDATASCALE;
PCI:74h) for PMCSR[14:13], respectively.
The PCI 9030 supports only D
Power Management States. Therefore, the PMDATA
register, which provides operating data (such as
power consumption and/or heat dissipation), retains
only four possible power data combinations:
Each power combination field requires an 8-bit register
in which to store the data. The PCI 9030 provides a
32-bit hidden register, PMDATASEL, to store such
information. The PMDATASEL register can be written
only from the serial EEPROM and read from
PMDATA[7:0], with the corresponding value in the
Data_Select bits (PMCSR[12:9]).
Notes:
however, the version encoding in Power Management Version
bits (PMC[2:0]) indicates compliance with PCI Power Mgmt. r1.0.
PMC[2:0] can be programmed in serial EEPROM to the value 010 to
indicate compliance with PCI Power Mgmt. r1.1. (Refer to PCI 9030
Design Notes.)
The New Capability Pointer bits (CAP_PTR[7:0]) must always
contain the default value 40h. (Refer to PCI 9030 Errata #9.)
1. D
2. D
3. D
4. D
PCI Power Management Functional Description
The PCI 9030 complies with PCI Power Mgmt. r1.1;
0
3
0
3hot
specified
Power Consumed
Power Consumed
Power Dissipated
Power Management
Data_Select, Data_Scale,
and Power Data Utilization
© 2002 PLX Technology, Inc. All rights reserved.
3hot
Power Dissipated
, PCI Memory and I/O accesses are
in
PCI 9030 Data Book Version 1.4
the
0
, D
Data_Select
3hot
, and D
3cold
bits
.